Datasheet

AD5307/AD5317/AD5327
Rev. C | Page 5 of 28
AC CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V, R
L
= 2 k to GND, C
L
= 200 pF to GND. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
A, B Versions
1
Parameter
2, 3
Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time V
REF
= V
DD
= 5 V
AD5307 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0)
AD5317 7 9 μs 1/4 scale to 3/4 scale change (0x100 to 0x300)
AD5327 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00)
Slew Rate 0.7 V/μs
Major-Code Change Glitch Energy 12 nV-s 1 LSB change around major carry
Digital Feedthrough 0.5 nV-s
SDO Feedthrough 4 nV-s Daisy-chain mode; SDO load is 10 pF
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
REF
= 2 V ± 0.1 V p-p; unbuffered mode
Total Harmonic Distortion −70 dB V
REF
= 2.5 V ± 0.1 V p-p; frequency = 10 kHz
1
Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.
2
Guaranteed by design and characterization; not production tested.
3
See the Terminology section.
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
A, B Versions
Parameter
1, , 2
3
Limit at T
MIN
, T
MAX
Unit Conditions/Comments
t
1
33 ns min SCLK cycle time
t
2
13 ns min SCLK high time
t
3
13 ns min SCLK low time
t
4
13 ns min
SYNC to SCLK falling edge set-up time
t
5
5 ns min Data set-up time
t
6
4.5 ns min Data hold time
t
7
5 ns min
SCLK falling edge to
SYNC rising edge
t
8
50 ns min
Minimum
SYNC high time
t
9
20 ns min
LDAC pulse width
t
10
20 ns min
SCLK falling edge to
LDAC rising edge
t
11
20 ns min
CLR pulse width
t
12
0 ns min
SCLK falling edge to
LDAC falling edge
t
13
4, 5
20 ns max SCLK rising edge to SDO valid (V
DD
= 3.6 V to 5.5 V)
25 ns max SCLK rising edge to SDO valid (V
DD
= 2.5 V to 3.5 V)
t
14
5 ns min
SCLK falling edge to
SYNC rising edge
t
15
8 ns min
SYNC rising edge to SCLK rising edge
t
16
0 ns min
SYNC rising edge to LDAC falling edge
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 3 and Figure 4.
4
This is measured with the load circuit of Figure 2. t
13
determines maximum SCLK frequency in daisy-chain mode.
5
Daisy-chain mode only.