Datasheet

AD5307/AD5317/AD5327
Rev. C | Page 4 of 28
A Version
1
B Version
Parameter
2
Min Typ Max Min Typ Max Unit Conditions/Comments
LOGIC INPUTS
Input Current ±1 ±1 mA
Input Low Voltage, V
IL
0.8 0.8 V V
DD
= 5 V ± 10%
0.6 0.6 V V
DD
= 3 V ± 10%
0.5 0.5 V V
DD
= 2.5 V
Input High Voltage, V
IH
(Excluding DCEN)
1.7 1.7 V V
DD
= 2.5 V to 5.5 V; TTL and
1.8 V CMOS compatible
Input High Voltage, V
IH
(DCEN)
2.4 2.4 V
DD
= 5 V ± 10%
2.1 2.1 V V
DD
= 3 V ± 10%
2.0 2.0 V V
DD
= 2.5 V
Pin Capacitance 3 3 pF
LOGIC OUTPUT (SDO)
V
DD
= 4.5 V to 5.5 V
Output Low Voltage, V
OL
0.4 0.4 V I
SINK
= 2 mA
Output High Voltage, V
OH
V
DD
− 1 V
DD
− 1 V I
SOURCE
= 2 mA
V
DD
= 2.5 V to 3.6 V
Output Low Voltage, V
OL
0.4 0.4 V I
SINK
= 2 mA
Output High Voltage, V
OH
V
DD
−
0.5
V
DD
−
0.5
V I
SOURCE
= 2 mA
Floating State Leakage Current ±1 ±1 μA DCEN = GND
Floating State Output Capacitance 3 3 pF DCEN = GND
POWER REQUIREMENTS
V
DD
2.5 5.5 2.5 5.5 V
I
DD
(Normal Mode)
8
V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V 500 900 500 900 μA
V
DD
= 2.5 V to 3.6 V 400 750 400 750 μA
All DACs in unbuffered mode; in
buffered mode, extra current is
typically x mA per DAC, where
x = 5 mA + V
REF
/R
DAC
I
DD
(Power-Down Mode) V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V 0.3 1 0.3 1 μA
V
DD
= 2.5 V to 3.6 V 0.09 1 0.09 1 μA
1
Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.
2
See the Terminology section.
3
DC specifications tested with the outputs unloaded, unless otherwise noted.
4
Linearity is tested using a reduced code range: AD5307 (Code 8 to Code 255); AD5317 (Code 28 to Code 1023); AD5327 (Code 115 to Code 4095).
5
This corresponds to x codes, where x = deadband voltage/LSB size.
6
Guaranteed by design and characterization; not production tested.
7
For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V
REF
= V
DD
and offset plus
gain error must be positive.
8
Interface inactive. All DACs active. DAC outputs unloaded.