Datasheet
AD5307/AD5317/AD5327
Rev. C | Page 21 of 28
OPTO-ISOLATED INTERFACE FOR
PROCESS-CONTROL APPLICATIONS
The AD5307/AD5317/AD5327 each have a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process-control and industrial applications. Due to noise, safety
requirements, or distance, it may be necessary to isolate the
AD5307/AD5317/AD5327 from the controller. This can easily
be achieved by using opto-isolators capable of providing isolation
in excess of 3 kV. The actual data rate achieved can be limited
by the type of optocouplers chosen. The serial loading structure
of the AD5307/AD5317/AD5327 makes them ideally suited for
use in opto-isolated applications.
Figure 43 shows an opto-isolated
interface to the AD5307/AD5317/AD5327 where DIN, SCLK,
and
SYNC
are driven from optocouplers. The power supply to
the part should also be isolated. This is done by using a trans-
former. On the DAC side of the transformer, a 5 V regulator
provides the 5 V supply required for the AD5307/AD5317/
AD5327.
10kΩ
DIN
GND
SCLK
5V
REGULATOR
POWER
10kΩ
10kΩ
AD5307
DCEN
02067-043
SYNC
V
OUT
B
V
OUT
C
V
OUT
D
V
REF
AB
V
REF
CD
10µF
0.1µF
V
OUT
A
V
DD
V
DD
V
DD
V
DD
SCLK
DIN
SYN
C
Figure 43. AD5307 in an Opto-Isolated Interface
DECODING MULTIPLE
AD5307/AD5317/AD5327 DEVICES
The
SYNC
pin on the AD5307/AD5317/AD5327 can be used in
applications to decode a number of DACs. In this application,
all DACs in the system receive the same serial clock and serial
data, but the
SYNC
to only one of the devices is active at any
given time, allowing access to four channels in this 16-channel
system. The 74HC139 is used as a 2-to-4 line decoder to address
any of the DACs in the system. To prevent timing errors, the
enable input should be brought to its inactive state while the
coded address inputs are changing state.
Figure 44 shows a
diagram of a typical setup for decoding multiple AD5307
devices in a system.
74HC139
ENABLE
CODED
A
DDRESS
1G
1A
1B
DGND
1Y0
1Y1
1Y2
1Y3
SCLK
DIN
DIN
SCLK
DIN
SCLK
DIN
SCLK
DIN
SCLK
AD5307
AD5307
AD5307
AD5307
V
OUT
B
V
OUT
C
V
OUT
D
V
OUT
A
SYNC
SYNC
SYNC
V
CC
V
DD
V
OUT
B
V
OUT
C
V
OUT
D
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
V
OUT
A
02067-044
SYNC
Figure 44. Decoding Multiple AD5307 Devices in a System
AD5307/AD5317/AD5327 AS DIGITALLY
PROGRAMMABLE WINDOW DETECTORS
A digitally programmable upper/lower limit detector using two of
the DACs in the AD5307/AD5317/AD5327 is shown in
Figure 45.
The upper and lower limits for the test are loaded to DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the V
IN
input is not within the programmed window,
an LED indicates the fail condition. Similarly, DAC C and DAC D
can be used for window detection on a second V
IN
signal.
5V
SCLK
DIN
1/2
CMP04
1kΩ
FAIL
1kΩ
PASS
1/6 74HC05
SYNC
10µF0.1µF
V
REF
V
IN
PASS/FAIL
AD5307/
AD5317/
AD5327
SCLK
DIN
GND
V
OUT
A
V
REF
AB
V
REF
CD
V
OUT
B
SYNC
V
DD
02067-045
Figure 45. Window Detection