Datasheet

AD5307/AD5317/AD5327
Rev. C | Page 17 of 28
SERIAL INTERFACE
The AD5307/AD5317/AD5327 are controlled over versatile 3-wire
serial interfaces that operate at clock rates of up to 30 MHz and
are compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in
Figure 3. The 16-bit word consists of four control bits followed
by 8, 10, or 12 bits of DAC data, depending on the device type.
Data is loaded MSB first (Bit 15), and the first two bits
determine whether the data is for DAC A, DAC B, DAC C, or
DAC D. Bit 13 and Bit 12 control the operating mode of the
DAC. Bit 13 is GAIN, which determines the output range of the
part. Bit 12 is BUF, which controls whether the reference inputs
are buffered or unbuffered.
Table 6. Address Bits for the AD53x7
A1 (Bit 15) A0 (Bit 14) DAC Addressed
0 0 DAC A
0 1 DAC B
1 0 DAC C
1 1 DAC D
CONTROL BITS
GAIN controls the output range of the addressed DAC.
0: output range of 0 V to V
REF
.
1: output range of 0 V to 2 V
REF
.
BUF controls whether reference of the addressed DAC is
buffered or unbuffered.
0: unbuffered reference.
1: buffered reference.
The AD5327 uses all 12 bits of DAC data; the AD5317 uses
10 bits and ignores the 2 LSBs. The AD5307 uses eight bits and
ignores the last four bits. The data format is straight binary, with
all 0s corresponding to 0 V output and all 1s corresponding to
full-scale output (V
REF
− 1 LSB).
The
SYNC
input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can be transferred
into the device only while
SYNC
is low. To start the serial data
transfer,
SYNC
should be taken low, observing the minimum
SYNC
to SCLK falling edge set-up time, t
4
. After
SYNC
goes
low, serial data is shifted into the device’s input shift register on
the falling edges of SCLK for 16 clock pulses. In standalone
mode (DCEN = 0), any data and clock pulses after the 16th
falling edge of SCLK are ignored, and no further serial data
transfer can occur until
SYNC
is taken high and low again.
SYNC
can be taken high after the falling edge of the 16th SCLK
pulse, observing the minimum SCLK falling edge to
SYNC
rising edge time, t
7
.
After the end of serial data transfer, data is automatically trans-
ferred from the input shift register to the input register of the
selected DAC. If
SYNC
is taken high before the 16th falling
edge of SCLK, the data transfer is aborted and the DAC input
registers are not updated.
When data has been transferred into the input register of a DAC,
the corresponding DAC register and DAC output can be updated
by taking
LDAC
low.
CLR
is an active low, asynchronous clear
that clears the input registers and DAC registers to all 0s.
BIT 15
(MSB)
BIT 0
(LSB)
A1 BUF D7 D6 D5 D4 D3 D2 D1 D0GAINA0 XXXX
DATA BITS
02067-033
Figure 33. AD5307 Input Shift Register Contents
BIT 15
(MSB)
BIT 0
(LSB)
A1 BUF D9 D8 D7 D6 D5 D4 D3 D2GAINA0 D1 D0 X X
DATA BITS
02067-034
Figure 34. AD5317 Input Shift Register Contents
BIT 15
(MSB)
BIT 0
(LSB)
A1 BUF D11 D10 D9 D8 D7 D6 D5 D4GAINA0 D3 D2 D1 D0
DATA BITS
02067-035
Figure 35. AD5327 Input Shift Register Contents