Datasheet
2.5 V to 5.5 V, 400 μA, Quad Voltage Output,
8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5307/AD5317/AD5327
Rev. C
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FEATURES
AD5307: 4 buffered 8-bit DACs in 16-lead TSSOP
A version: ±1 LSB INL; B version: ±0.625 LSB INL
AD5317: 4 buffered 10-bit DACs in 16-lead TSSOP
A version: ±4 LSB INL; B version: ±2.5 LSB INL
AD5327: 4 buffered 12-bit DACs in 16-lead TSSOP
A version: ±16 LSB INL; B version: ±10 LSB INL
Low power operation: 400 μA @ 3 V, 500 μA @ 5 V
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power down to 90 nA @ 3 V, 300 nA @ 5 V (
LDAC
pin)
Double-buffered input logic
Buffered/unbuffered reference input options
Output range: 0 V to V
REF
or 0 V to 2 V
REF
Power-on reset to 0 V
Simultaneous update of outputs (
LDAC
pin)
Asynchronous clear facility (
CLR
pin)
Low power, SPI®-, QSPI™-, MICROWIRE™-, and DSP-
compatible 3-wire serial interface
SDO daisy-chaining option
On-chip rail-to-rail output buffer amplifiers
Temperature range of −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5307/AD5317/AD5327
1
are quad 8-,10-,12-bit buffered
voltage-output DACs in 16-lead TSSOP that operate from single
2.5 V to 5.5 V supplies and consume 400 A at 3 V. Their on-
chip output amplifiers allow the outputs to swing rail-to-rail with
a slew rate of 0.7 V/s. The AD5307/AD5317/AD5327 utilize
versatile 3-wire serial interfaces that operate at clock rates up to
30 MHz; these parts are compatible with standard SPI, QSPI,
MICROWIRE, and DSP interface standards.
The references for the four DACs are derived from two reference
pins (one per DAC pair). These reference inputs can be configured
as buffered or unbuffered inputs. Each part incorporates a power-
on reset circuit, ensuring that the DAC outputs power up to 0 V
and remain there until a valid write to the device takes place.
There is also an asynchronous active low
CLR
pin that clears all
DACs to 0 V. The outputs of all DACs can be updated simul-
taneously using the asynchronous
LDAC
input. Each part
contains a power-down feature that reduces the current
consumption of the device to 300 nA @ 5 V (90 nA @ 3 V). The
parts can also be used in daisy-chaining applications using the
SDO pin.
All three parts are offered in the same pinout, allowing users to
select the amount of resolution appropriate for their application
without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
REF
AB
V
REF
CD
POWER-ON
RESET
POWER-DOWN
LOGIC
GND
AD5307/AD5317/AD5327
LDAC
PDLDAC CLRDCEN
SDO
DIN
SYNC
SCLK
BUFFER
BUFFER
BUFFER
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
V
OUT
D
V
OUT
C
V
OUT
B
V
OUT
A
GAIN-SELECT
LOGIC
INTERFACE
LOGIC
02067-001
Figure 1.
1
Protected by U.S. Patent No. 5,969,657; other patents pending.