Datasheet

AD5306/AD5316/AD5326
Rev. F | Page 19 of 24
However, if the master sends an ACK and continues clocking
SCL (no stop is sent), the DAC retransmits the same two bytes
of data on SDA. This allows continuous readback of data from
the selected DAC register.
Alternatively, the user can send a start followed by the address
with R/
W
= 1. In this case, the previously loaded pointer
settings are used and readback of data can start immediately.
DOUBLE-BUFFERED INTERFACE
The AD5306/AD5316/AD5326 DACs have double-buffered
interfaces consisting of two banks of registers: input registers
and DAC registers. The input registers are connected directly to
the input shift register and the digital code is transferred to the
relevant input register on completion of a valid write sequence.
The DAC registers contain the digital code used by the resistor
strings.
Access to the DAC registers is controlled by the
LDAC
pin.
When
LDAC
is high, the DAC registers are latched and the
input registers can change state without affecting the contents of
the DAC registers. When
LDAC
is low, however, the DAC
registers become transparent and the contents of the input
registers are transferred to them.
Double-buffering is useful if the user requires simultaneous
updating of all DAC outputs. The user may write to each of the
input registers individually and then, by pulsing the
LDAC
input low, all outputs update simultaneously.
These parts contain an extra feature whereby a DAC register is
not updated unless its input register has been updated since the
last time that
LDAC
was low. Normally, when
LDAC
is low, the
DAC registers are filled with the contents of the input registers.
In the AD5306/AD5316/AD5326, the part updates the DAC
register only if the input register has been changed since the last
time the DAC register was updated, thereby removing
unnecessary digital crosstalk.
LOAD DAC INPUT LDAC
LDAC
transfers data from the input registers to the DAC
registers and, therefore, updates the outputs. The
LDAC
function enables double-buffering of the DAC data, GAIN,
and BUF. There are two
LDAC
modes: synchronous mode and
asynchronous mode.
In synchronous mode, the DAC registers are updated after new
data is read in on the rising edge of the eighth SCL pulse.
LDAC
can be tied permanently low or pulsed as in
Figure 2.
In asynchronous mode, the outputs are not updated at the same
time the input registers are written to. When
LDAC
goes low,
the DAC registers are updated with the contents of the input
registers.
POWER-DOWN MODE
The AD5306/AD5316/AD5326 have very low power consump-
tion, dissipating typically at 1.2 mW with a 3 V supply and
2.5 mW with a 5 V supply. Power consumption can be reduced
further when the DACs are not in use by putting them into
power-down mode, which is selected by setting the
PD
pin low
or by setting Bit 12 (
PD
) of the data-word to 0.
When the
PD
pin is high and the
PD
bit is set to 1, all DACs work
normally with a typical power consumption of 500 μA at 5 V
(400 μA at 3 V). In power-down mode, however, the supply
current falls to 300 nA at 5 V (90 nA at 3 V) when all DACs are
powered down. Not only does the supply current drop, but each
output stage is internally switched from the output of its ampli-
fier, making it open-circuit. This has the advantage that the
outputs are three-state while the part is in power-down mode
and provides a defined input condition for whatever is connected
to the output of the DAC amplifiers. The output stage is shown
in
Figure 35.
POWER-DOWN
CIRCUITRY
RESISTOR
STRING DAC
02066-035
AMPLIFIER
V
OUT
Figure 35. Output Stage During Power-Down
The bias generator, output amplifiers, resistor strings, and all
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the registers
are unaffected when in power-down. In fact, it is possible to
load new data into the input registers and DAC registers during
power-down. The DAC outputs update as soon as the
PD
pin
goes high or the
PD
bit is reset to 1. The time to exit power-
down is typically 2.5 μs for V
DD
= 5 V and 5 μs for V
DD
= 3 V.
This is the time from the rising edge of the eighth SCL pulse or
from the rising edge of
PD
to when the output voltage deviates
from its power-down voltage (see
Figure 23).