Datasheet

AD5305/AD5315/AD5325
Rev. G | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10
9
8
7
6
1
2
3
4
5
GND
SDA
SCL
REFIN
A0
AD5305/
AD5315/
AD5325
TOP VIEW
(Not to Scale)
V
DD
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
00930-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
DD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND.
2 V
OUT
A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
3 V
OUT
B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
4 V
OUT
C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V
DD
.
6 V
OUT
D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
7 GND Ground Reference Point for All Circuitry on the Part.
8 SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift
register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up
resistor.
9 SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift
register. Clock rates of up to 400 kb/s can be accommodated in the 2-wire interface.
10 A0 Address Input. Sets the least significant bit of the 7-bit slave address.