Datasheet

AD5305/AD5315/AD5325
Rev. G | Page 5 of 24
AC CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V, R
L
= 2 k to GND, C
L
= 200 pF to GND, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
A, B Version
1
Parameter
2, 3
Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time V
REF
= V
DD
= 5 V
AD5305 6 8 μs ¼ scale to ¾ scale change (0×40 to 0×C0)
AD5315 7 9 μs ¼ scale to ¾ scale change (0×100 to 0×300)
AD5325 8 10 μs ¼ scale to ¾ scale change (0×400 to 0×C00)
Slew Rate 0.7 V/μs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB change around major carry
Digital Feedthrough 1 nV-s
Digital Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
REF
= 2 V ± 0.1 V p-p
Total Harmonic Distortion −70 dB V
REF
= 2.5 V ± 0.1 V p-p, frequency = 10 kHz
1
Temperature range (A, B version): −40°C to +105°C; typical at +25°C.
2
Guaranteed by design and characterization, not production tested.
3
See the Terminology section.
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1, 2
Limit at T
MIN
, T
MAX
(A, B Version) Unit Conditions/Comments
f
SCL
400 kHz max SCL clock frequency
t
1
2.5 μs min SCL cycle time
t
2
0.6 μs min t
HIGH
, SCL high time
t
3
1.3 μs min t
LOW
, SCL low time
t
4
0.6 μs min t
HD,STA
, start/repeated start condition hold time
t
5
100 ns min t
SU,DAT
, data setup time
t
6
3
0.9 μs max t
HD,DAT
, data hold time
0 μs min t
HD,DAT
, data hold time
t
7
0.6 μs min t
SU,STA
, setup time for repeated start
t
8
0.6 μs min t
SU,STO
, stop condition setup time
t
9
1.3 μs min t
BUF
, bus-free time between a stop and a start condition
t
10
300 ns max t
R
, rise time of SCL and SDA when receiving
0 ns min t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
11
250 ns max t
F
, fall time of SDA when transmitting
0 ns min t
F
, fall time of SDA when receiving (CMOS compatible)
300 ns max t
F
, fall time of SCL and SDA when receiving
20 + 0.1 C
B
4
ns min t
F
, fall time of SCL and SDA when transmitting
C
B
4
400 pF max Capacitive load for each bus line
1
See Figure 2.
2
Guaranteed by design and characterization; not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
IH
min of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
4
C
B
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.