Datasheet
AD5305/AD5315/AD5325
Rev. G | Page 4 of 24
A Version
1
B Version
1
Parameter
2
Min Typ Max Min Typ Max Unit Conditions/Comments
LOGIC INPUTS (A0)
5
Input Current ±1 ±1 μA
Input Low Voltage, V
IL
0.8 0.8 V V
DD
= 5 V ± 10%
0.6 0.6 V V
DD
= 3 V ± 10%
0.5 0.5 V V
DD
= 2.5 V
Input High Voltage, V
IH
2.4 2.4 V V
DD
= 5 V ± 10%
2.1 2.1 V V
DD
= 3 V ± 10%
2.0 2.0 V V
DD
= 2.5 V
Pin Capacitance 3 3 pF
LOGIC INPUTS (SCL, SDA)
5
Input High Voltage, V
IH
0.7
V
DD
V
DD
+
0.3
0.7
V
DD
V
DD
+
0.3
V SMBus compatible at V
DD
< 3.6 V
Input Low Voltage, V
IL
−0.3 0.3 V
DD
−0.3 0.3 V
DD
V SMBus compatible at V
DD
< 3.6 V
Input Leakage Current, I
IN
±1 ±1 μA
Input Hysteresis, V
HYST
0.05
V
DD
0.05
V
DD
V
Input Capacitance, C
IN
8 8 pF
Glitch Rejection 50 50 ns
Input filtering suppresses noise spikes
of less than 50 ns
LOGIC OUTPUT (SDA)
5
Output Low Voltage, V
OL
0.4 0.4 V I
SINK
= 3 mA
0.6 0.6 V I
SINK
= 6 mA
Three-State Leakage Current ±1 ±1 μA
Three-State Output
Capacitance
8 8 pF
POWER REQUIREMENTS
V
DD
2.5 5.5 2.5 5.5 V
I
DD
(Normal Mode)
7
V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V 600 900 600 900 μA
V
DD
= 2.5 V to 3.6 V 500 700 500 700 μA
I
DD
(Power-Down Mode) V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V 0.2 1 0.2 1 μA
I
DD
= 4 μA (maximum) during
0 readback on SDA
V
DD
= 2.5 V to 3.6 V 0.08 1 0.08 1 μA
I
DD
= 1.5 μA (maximum) during
0 readback on SDA
1
Temperature range (A, B version): −40°C to +105°C; typical at +25°C.
2
See the Terminology section.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).
5
Guaranteed by design and characterization, not production tested.
6
For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V
REF
= V
DD
and offset plus gain error must be
positive.
7
I
DD
specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.