Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) MSOP 10

2.5 V to 5.5 V, 500 μA, 2-Wire Interface

Quad Voltage Output, 8-/10-/12-Bit DACs

AD5305/AD5315/AD5325

Rev. G

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FEATURES

AD5305: 4 buffered 8-bit DACs in 10-lead MSOP

A version: ±1 LSB INL, B version: ±0.625 LSB INL

AD5315: 4 buffered 10-bit DACs in 10-lead MSOP

A version: ±4 LSB INL, B version: ±2.5 LSB INL

AD5325: 4 buffered 12-bit DACs in 10-lead MSOP

A version: ±16 LSB INL, B version: ±10 LSB INL

Low power operation: 500 μA @ 3 V, 600 μA @ 5 V

2-wire (I

C®-compatible) serial interface

2.5 V to 5.5 V power supply

Guaranteed monotonic by design over all codes

Power-down to 80 nA @ 3 V, 200 nA @ 5 V

Three power-down modes

Double-buffered input logic

Output range: 0 V to V

REF

Power-on reset to 0 V

Simultaneous update of outputs (

LDAC

function)

Software clear facility

Data readback facility

On-chip rail-to-rail output buffer amplifiers

Temperature range: −40°C to +105°C

APPLICATIONS

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

Industrial process control

GENERAL DESCRIPTION

The AD5305/AD5315/AD5325

are quad 8-, 10-, and 12-bit

buffered voltage output DACs in a 10-lead MSOP that operate

from a single 2.5 V to 5.5 V supply, consuming 500 A at 3 V.

Their on-chip output amplifiers allow rail-to-rail output swing

with a slew rate of 0.7 V/s. A 2-wire serial interface that

operates at clock rates up to 400 kHz is used. This interface is

SMBus compatible at V

< 3.6 V. Multiple devices can be

placed on the same bus.

The references for the four DACs are derived from one

reference pin. The outputs of all DACs can be updated

simultaneously using the software LDAC function.

The parts incorporate a power-on reset circuit, which ensures

that the DAC outputs power up to 0 V and remain there until a

valid write takes place to the device. There is also a software

clear function to reset all input and DAC registers to 0 V. The

parts contain a power-down feature that reduces the current

consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).

The low power consumption of these parts in normal operation

makes them ideally suited for portable battery-operated equip-

ment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V,

reducing to 1 µW in power-down mode.

Protected by U.S. Patent No. 5,969,657 and 5,684,481.

FUNCTIONAL BLOCK DIAGRAM

REF IN

GND

AD5305/AD5315/AD5325

SCL

BUFFER

INPUT

LDAC

POWER-ON

RESET

INTERFACE

LOGIC

POWER-DOWN

LOGIC

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

DAC

00930-001

OUT

Figure 1.

Summary of content (24 pages)

PAGE 1
2.5 V to 5.5 V, 500 μA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs AD5305/AD5315/AD5325 FEATURES GENERAL DESCRIPTION AD5305: 4 buffered 8-bit DACs in 10-lead MSOP A version: ±1 LSB INL, B version: ±0.625 LSB INL AD5315: 4 buffered 10-bit DACs in 10-lead MSOP A version: ±4 LSB INL, B version: ±2.5 LSB INL AD5325: 4 buffered 12-bit DACs in 10-lead MSOP A version: ±16 LSB INL, B version: ±10 LSB INL Low power operation: 500 μA @ 3 V, 600 μA @ 5 V 2-wire (I2C®-compatible) serial interface 2.
PAGE 2
AD5305/AD5315/AD5325 TABLE OF CONTENTS Features .............................................................................................. 1 Read/Write Sequence................................................................. 16 Applications....................................................................................... 1 Pointer Byte Bits ......................................................................... 16 General Description ..........................................................
PAGE 3
AD5305/AD5315/AD5325 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. Table 1. 2 Parameter DC PERFORMANCE 3, 4 AD5305 Resolution Relative Accuracy Differential Nonlinearity Min A Version 1 Typ Max Min B Version1 Typ Max Unit 8 ±0.15 ±0.02 ±1 ±0.25 8 ±0.15 ±0.02 ±0.625 ±0.25 Bits LSB LSB AD5315 Resolution Relative Accuracy Differential Nonlinearity 10 ±0.5 ±0.05 ±4 ±0.5 10 ±0.5 ±0.05 ±2.5 ±0.
PAGE 4
AD5305/AD5315/AD5325 2 Parameter LOGIC INPUTS (A0)5 Input Current Input Low Voltage, VIL Input High Voltage, VIH Pin Capacitance LOGIC INPUTS (SCL, SDA)5 Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIN Input Hysteresis, VHYST Min A Version 1 Typ Max ±1 0.8 0.6 0.5 2.4 2.1 2.0 Conditions/Comments ±1 0.8 0.6 0.5 μA V V V V V V pF VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V VDD + 0.3 0.3 VDD ±1 V SMBus compatible at VDD < 3.
PAGE 5
AD5305/AD5315/AD5325 AC CHARACTERISTICS VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. Table 2. 2, 3 Parameter Output Voltage Settling Time AD5305 AD5315 AD5325 Slew Rate Major-Code Transition Glitch Energy Digital Feedthrough Digital Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion A, B Version 1 Min Typ Max Unit 6 7 8 0.
PAGE 6
AD5305/AD5315/AD5325 SDA t9 t3 t11 t10 t4 SCL t6 t2 t7 t5 REPEATED START CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram Rev.
PAGE 7
AD5305/AD5315/AD5325 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter1 VDD to GND SCL, SDA to GND A0 to GND Reference Input Voltage to GND VOUTA to VOUTD to GND Operating Temperature Range Industrial (A, B Version) Storage Temperature Range Junction Temperature (TJ max) MSOP Power Dissipation θJA Thermal Impedance θJC Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating –0.3 V to +7 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V –0.
PAGE 8
AD5305/AD5315/AD5325 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VOUTA 2 VOUTB 3 VOUTC 4 REFIN 5 AD5305/ AD5315/ AD5325 TOP VIEW (Not to Scale) 10 A0 9 SCL 8 SDA 7 GND 6 VOUTD 00930-003 VDD 1 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD VOUTA VOUTB VOUTC REFIN VOUTD GND SDA 9 SCL 10 A0 Description Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND.
PAGE 9
AD5305/AD5315/AD5325 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 0.2 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 0.1 0 –0.1 –0.5 0 50 100 150 200 250 CODE –0.3 00930-006 –1.0 0 150 200 250 Figure 7. AD5305 Typical DNL Plot 3 0.6 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 2 0.4 1 0.2 DNL ERROR (LSB) 0 –1 –2 0 –0.2 –0.4 200 400 600 800 1000 CODE –0.6 00930-007 0 0 200 400 600 800 1000 CODE Figure 5.
PAGE 10
AD5305/AD5315/AD5325 0.50 0.2 VDD = 5V TA = 25°C 0.25 GAIN ERROR 0 MAXINL MAXDNL ERROR (%) ERROR (LSB) TA = 25°C VREF = 2V 0.1 0 MIN DNL –0.25 –0.1 –0.2 –0.3 –0.4 OFFSET ERROR 0 1 2 3 4 5 VREF (V) –0.6 00930-012 –0.50 0 Figure 10. AD5305 INL and DNL Error vs. VREF 1 2 3 VDD (V) 4 5 6 00930-015 –0.5 MIN INL Figure 13. Offset Error and Gain Error vs. VDD 0.5 5 VDD = 5V VREF = 3V 0.4 0.3 5V SOURCE 4 MAX INL 3V SOURCE MAX DNL 0.1 3 VOUT (V) ERROR (LSB) 0.
PAGE 11
AD5305/AD5315/AD5325 600 TA = 25°C VDD = 5V VREF = 5V –40°C 500 CH1 +25°C 400 VOUTA IDD (µA) +105°C 300 200 SCL CH2 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 Figure 16. Supply Current vs. Supply Voltage CH1 1V, CH2 5V, TIME BASE = 1µs/DIV 00930-021 0 2.5 00930-018 100 Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Change) 0.5 TA = 25°C VDD = 5V VREF = 2V 0.4 CH1 VDD IDD (µA) 0.3 –40°C 0.2 +25°C VOUTA CH2 0.1 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.
PAGE 12
AD5305/AD5315/AD5325 0.02 350 VDD = 5V 400 450 IDD (µA) 500 550 600 0.01 0 –0.01 –0.02 Figure 22. IDD Histogram with VDD = 3 V and VDD = 5 V 0 1 2 3 VREF (V) 4 5 6 00930-027 300 FULL SCALE ERROR (V) VDD = 3V 00930-024 FREQUENCY VDD = 5V TA = 25°C Figure 25. Full-Scale Error vs. VREF 2.50 VOUT (V) 1mV/DIV 2.49 2.47 1µs/DIV 50ns/DIV Figure 23. AD5325 Major-Code Transition Glitch Energy Figure 26.
PAGE 13
AD5305/AD5315/AD5325 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus code plots can be seen in Figure 4, Figure 5, and Figure 6. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 14
AD5305/AD5315/AD5325 GAIN ERROR PLUS OFFSET ERROR GAIN ERROR PLUS OFFSET ERROR ACTUAL OUTPUT VOLTAGE IDEAL IDEAL ACTUAL NEGATIVE OFFSET ERROR POSITIVE OFFSET DAC CODE DAC CODE Figure 28. Transfer Function with Positive Offset DEAD BAND CODES AMPLIFIER FOOTROOM (1mV) 00930-004 NEGATIVE OFFSET ERROR Figure 27. Transfer Function with Negative Offset Rev.
PAGE 15
AD5305/AD5315/AD5325 FUNCTIONAL DESCRIPTION The AD5305/AD5315/AD5325 are quad resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. Each contains four output buffer amplifiers and is written to via a 2-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/μs. The four DACs share a single reference input pin.
PAGE 16
AD5305/AD5315/AD5325 READ/WRITE SEQUENCE 2 The AD5305/AD5315/AD5325 are controlled via an I C compatible serial bus. The DACs are connected to this bus as slave devices (that is, no clock is generated by the AD5305/ AD5315/AD5325 DACs). This interface is SMBus compatible at VDD < 3.6 V. The AD5305/AD5315/AD5325 have a 7-bit slave address. The 6 MSB are 000110 and the LSB is determined by the state of the A0 pin.
PAGE 17
AD5305/AD5315/AD5325 Table 7. CLR and LDAC Bit Descriptions WRITE OPERATION Bit CLR When writing to the AD5305/AD5315/AD5325 DACs, the user must begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte is followed by the pointer byte, which is also acknowledged by the DAC. Two bytes of data are then written to the DAC, as shown in Figure 33. A stop condition follows.
PAGE 18
AD5305/AD5315/AD5325 SCL 0 SDA 0 0 1 START COND BY MASTER 1 0 A0 R/W X X ACK MSB BY AD53x5 ADDRESS BYTE LSB POINTER BYTE ACK BY AD53x5 SCL SDA 0 REPEATED START COND BY MASTER 0 0 1 1 0 A0 MSB R/W LSB ACK BY AD53x5 ADDRESS BYTE DATA BYTE ACK BY MASTER SCL MSB LSB LEAST SIGNIFICANT DATA BYTE NO ACK BY MASTER STOP COND BY MASTER NOTE: DATA BYTES ARE THE SAME AS THOSE IN THE WRITE SEQUENCE EXCEPT THAT DON’T CARES ARE READ BACK AS 0s. 00930-034 SDA Figure 34.
PAGE 19
AD5305/AD5315/AD5325 RESISTOR STRING DAC VOUT AMPLIFIER POWER-DOWN CIRCUITRY RESISTOR NETWORK 00930-035 When both bits are set to 0, the DAC works normally with its normal power consumption of 600 μA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (80 nA at 3 V). Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values.
PAGE 20
AD5305/AD5315/AD5325 APPLICATIONS TYPICAL APPLICATION CIRCUIT BIPOLAR OPERATION The AD5305/AD5315/AD5325 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0 V to VDD. More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780 and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference is the AD589, a 1.
PAGE 21
AD5305/AD5315/AD5325 AD5305/AD5315/AD5325 AS A DIGITALLY PROGRAMMABLE WINDOW DETECTOR POWER SUPPLY DECOUPLING A digitally programmable upper/lower limit detector using two of the DACs in the AD5305/AD5315/AD5325 is shown in Figure 39. The upper and lower limits for the test are loaded to DAC A and DAC B, which, in turn, set the limits on the CMP04. If the signal at the VIN input is not within the programmed window, an LED indicates the fail condition.
PAGE 22
AD5305/AD5315/AD5325 Table 9. Overview of All AD53xx Serial Devices Part No. SINGLES AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 DUALS AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 QUADS AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 OCTALS AD5308 AD5318 AD5328 Resolution No. of DACs DNL Interface Settling Time (μs) Package Pins 8 10 12 8 10 12 1 1 1 1 1 1 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.
PAGE 23
AD5305/AD5315/AD5325 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 6 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 1.10 MAX 0.33 0.17 SEATING PLANE 0.23 0.08 8° 0° 0.80 0.60 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 41.
PAGE 24
AD5305/AD5315/AD5325 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00930-0-5/06(G) Rev.