Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- TABLE OF CONTENTS
- REVISION HISTORY
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- TERMINOLOGY
- THEORY OF OPERATION
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS

Data Sheet AD5304/AD5314/AD5324
Rev. H | Page 5 of 24
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
V
DD
= 2.5 V to 3.6 V V
DD
= 3.6 V to 5.5 V Unit Test Conditions/Comments
t
1
40 33 ns min SCLK cycle time
t
2
16 13 ns min SCLK high time
t
3
16 13 ns min SCLK low time
t
4
16 13 ns min
SYNC
to SCLK falling edge setup time
t
5
5 5 ns min Data setup time
t
6
4.5 4.5 ns min Data hold time
t
7
0 0 ns min
SCLK falling edge to SYNC
rising edge
t
8
80 33 ns min
Minimum SYNC
high time
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90 % of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 2.
SCLK
DIN DB15
DB0
t
1
t
3
t
2
t
7
t
5
t
4
t
6
t
8
SYNC
00929-002
Figure 2. Serial Interface Timing Diagram