Datasheet

AD5302/AD5312/AD5322
Rev. D | Page 5 of 24
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V, all specifications T
MIN
to T
MAX
, unless otherwise noted.
1, 2, 3
Table 3.
Parameter Limit at T
MIN
, T
MAX
(A, B Version) Unit Conditions/Comments
t
1
33 ns min SCLK Cycle Time
t
2
13 ns min SCLK High Time
t
3
13 ns min SCLK Low Time
t
4
0 ns min
SYNC
to SCLK Active Edge Setup Time
t
5
5 ns min Data Setup Time
t
6
4.5 ns min Data Hold Time
t
7
0 ns min
SCLK Falling Edge to SYNC
Rising Edge
t
8
100 ns min
Minimum SYNC
High Time
t
9
20 ns min
LDAC
Pulse Width
t
10
20
ns min
SCLK Falling Edge to LDAC
Rising Edge
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 2.
SCLK
DIN
1
DB15
DB0
1
SEE INPUT SHIFT REGISTER SECTION.
t
1
t
3
t
2
t
7
t
9
t
10
t
5
t
4
t
6
t
8
LDA
C
LDA
C
S
YN
C
00928-002
Figure 2. Serial Interface Timing Diagram