Datasheet

AD5302/AD5312/AD5322
Rev. D | Page 19 of 24
OPTO-ISOLATED INTERFACE FOR PROCESS
CONTROL APPLICATIONS
Each AD5302/AD5312/AD5322 has a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process control and industrial applications. Due to noise, safety
requirements, or distance, it can be necessary to isolate the
AD5302/AD5312/AD5322 from the controller. This can easily
be achieved by using opto-isolators, which provide isolation in
excess of 3 kV. The serial loading structure of the AD5302/
AD5312/AD5322 makes them ideally suited for use in opto-
isolated applications. Figure 41 shows an opto-isolated interface
to the AD5302/AD5312/AD5322 where DIN, SCLK, and
SYNC
are driven from opto-couplers. The power supply to the part
also needs to be isolated by using a transformer. On the DAC
side of the transformer, a 5 V regulator provides the 5 V supply
required for the AD5302/AD5312/AD5322.
SCLK
DIN
AD5302/AD5312/
AD5322
00928-041
SYNC
GND
5V
REGULATOR
POWER
V
DD
10µF 0.1µF
V
OUT
A
V
OUT
B
V
REF
B
V
REF
A
V
DD
10kΩ
10kΩ
10kΩ
DIN
SYNC
SCLK
V
DD
V
DD
Figure 41. AD5302/AD5312/AD5322 in an Opto-Isolated Interface
DECODING MULTIPLE AD5302/AD5312/AD5322s
The
SYNC
pin on the AD5302/AD5312/AD5322 can be used in
applications to decode a number of DACs. In this application,
all the DACs in the system receive the same serial clock and serial
data, but only the
SYNC
to one of the devices is active at any one
time, allowing access to two channels in this eight-channel system.
The 74HC139 is used as a 2-to-4 line decoder to address any of
the DACs in the system. To prevent timing errors from occurring,
the enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 42 shows a
diagram of a typical setup for decoding multiple AD5302/
AD5312/AD5322 devices in a system.
74HC139
ENABLE
CODED
A
DDRESS
1G
1A
1B
DGND
1Y0
1Y1
1Y2
1Y3
SCLK
DIN
DIN
SCLK
DIN
SCLK
DIN
SCLK
DIN
SCLK
AD5302/AD5312/AD5322
SYNC
SYNC
SYNC
V
CC
00928-042
SYNC
AD5302/AD5312/AD5322
AD5302/AD5312/AD5322
AD5302/AD5312/AD5322
V
DD
Figure 42. Decoding Multiple AD5302/AD5312/AD5322 Devices in a System
AD5302/AD5312/AD5322 AS A DIGITALLY
PROGRAMMABLE WINDOW DETECTOR
Figure 43 shows a digitally programmable upper-/lower-limit
detector using the two DACs in the AD5302/AD5312/AD5322.
The upper and lower limits for the test are loaded to DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the V
IN
input is not within the programmed window,
an LED indicates the fail condition.
5
V
1/2
CMP04
FAIL PASS
1/6 74HC05
V
REF
SCLK
DIN
V
OUT
A
V
DD
00928-043
AD5302/AD5312/
AD5322
V
REF
A
GND
0.1µF 10µF
1kΩ 1kΩ
V
IN
PASS/ FAIL
DIN
SCLK
SYNC
SYNC
V
REF
B
V
OUT
B
Figure 43. Window Detector Using AD5302/AD5312/AD5322