Datasheet
AD5302/AD5312/AD5322
Rev. D | Page 17 of 24
MICROPROCESSOR INTERFACING
AD5302/AD5312/AD5322 TO ADSP-2101/ADSP-
2103 INTERFACE
Figure 34 shows a serial interface between the AD5302/AD5312/
AD5322 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-
2103 should be set up to operate in the SPORT transmit alternate
framing mode. The ADSP-2101/ADSP-2103 sport is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, 16-bit
word length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled. The data is clocked
out on each falling edge of the DSP’s serial clock and clocked into
the AD5302/AD5312/AD5322 on the rising edge of the DSP’s serial
clock. This corresponds to the falling edge of the DAC’s SCLK.
SCLK
DIN
SYNC
TFS
DT
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY
00928-034
AD5302/
AD5312/
AD5322
1
ADSP-2101/
ADSP-2103
1
Figure 34. AD5302/AD5312/AD5322 to ADSP-2101/ADSP-2103 Interface
AD5302/AD5312/AD5322 TO 68HC11/68L11
INTERFACE
Figure 35 shows a serial interface between the AD5302/AD5312/
AD5322 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5302/AD5312/AD5322,
while the MOSI output drives the serial data line of the DAC.
The
SYNC
signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
the 68HC11/68L11 should be configured so that its CPOL bit = 0
and its CPHA bit = 1. When data is being transmitted to the
DAC, the
SYNC
line is taken low (PC7). When the 68HC11/
68L11 are configured as above, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/ 68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data to the
AD5302/AD5312/AD5322, PC7 is left low after the first eight
bits are transferred and a second serial write operation is
performed to the DAC; PC7 is taken high at the end of this
procedure.
DIN
SCLK
SYNC
PC7
SCK
MOSI
68HC11/68L11
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
0
0
9
2
8
-
0
3
5
AD5302/
AD5312/
AD5322
1
Figure 35. AD5302/AD5312/AD5322 to 68HC11/68L11 Interface
AD5302/AD5312/AD5322 TO 80C51/80L51
INTERFACE
Figure 36 shows a serial interface between the AD5302/AD5312/
AD5322 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TXD of the 80C51/80L51 drives
SCLK of the AD5302/AD5312/AD5322, while RXD drives the
serial data line of the part. The
SYNC
signal is again derived
from a bit programmable pin on the port. In this case, port line
P3.3 is used. When data is to be transmitted to the AD5302/
AD5312/AD5322, P3.3 is taken low. The 80C51/80L51 transmit
data in 8-bit bytes only; thus only eight falling clock edges occur
in the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
output the serial data in a format that has the LSB first. The
AD5302/AD5312/AD5322 require their data with the MSB as
the first bit received. The 80C51/80L51 transmit routine should
take this into account.
DIN
SCLK
P3.3
TXD
RXD
80C51/80L51
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
00928-036
SYNC
AD5302/
AD5312/
AD5322
1
Figure 36. AD5302/AD5312/AD5322 to 80C51/80L51 Interface
AD5302/AD5312/AD5322 TO MICROWIRE
INTERFACE
Figure 37 shows an interface between the AD5302/AD5312/
AD5322 and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked
into the AD5302/AD5312/AD5322 on the rising edge of the SK.
DIN
SCLKSK
SO
MICROWIRE
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
00928-037
CS SYNC
AD5302/
AD5312/
AD5322
1
Figure 37. AD5302/AD5312/AD5322 to MICROWIRE Interface