Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) MSOP 10

2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail,

Voltage Output 8-/10-/12-Bit DACs

AD5302/AD5312/AD5322

Rev. D

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FEATURES

AD5302: Two 8-bit buffered DACs in 1 package

A version: ±1 LSB INL, B version: ±0.5 LSB INL

AD5312: Two 10-bit buffered DACs in 1 package

A version: ±4 LSB INL, B version: ±2 LSB INL

AD5322: Two 12-bit buffered DACs in 1 package

A version: ±16 LSB INL, B version: ±8 LSB INL

10-lead MSOP

Micropower operation: 300 μA @ 5 V (including

reference current)

Power-down to 200 nA @ 5 V, 50 nA @ 3 V

2.5 V to 5.5 V power supply

Double-buffered input logic

Guaranteed monotonic by design over all codes

Buffered/Unbuffered reference input options

0 V to V

REF

output voltage

Power-on-reset to 0 V

Simultaneous update of DAC outputs via

LDAC

Low power serial interface with Schmitt-triggered inputs

On-chip rail-to-rail output buffer amplifiers

Qualified for automotive applications

APPLICATIONS

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

GENERAL DESCRIPTION

The AD5302/AD5312/AD5322 are dual 8-, 10-, and 12-bit

buffered voltage output DACs in a 10-lead MSOP that operate

from a single 2.5 V to 5.5 V supply, consuming 230 A at 3 V.

Their on-chip output amplifiers allow the outputs to swing rail-

to-rail with a slew rate of 0.7 V/s. The AD5302/AD5312/AD5322

utilize a versatile 3-wire serial interface that operates at clock

rates up to 30 MHz and is compatible with standard SPI®,

QSPI™, MICROWIRE™, and DSP interface standards.

The references for the two DACs are derived from two reference

pins (one per DAC). The reference inputs can be configured as

buffered or unbuffered inputs. The outputs of both DACs can be

updated simultaneously using the asynchronous

LDAC

input.

The parts incorporate a power-on reset circuit, which ensures

that the DAC outputs power-up to 0 V and remain there until a

valid write takes place to the device. The parts contain a power-

down feature that reduces the current consumption of the

devices to 200 nA at 5 V (50 nA at 3 V) and provides software-

selectable output loads while in power-down mode.

The low power consumption of these parts in normal operation

makes them ideally suited for portable battery-operated

equipment. The power consumption is 1.5 mW at 5 V, 0.7 mW

at 3 V, reducing to 1 W in power-down mode.

FUNCTIONAL BLOCK DIAGRAM

DAC

RESISTOR

NETWORK

POWER-DOWN

LOGIC

RESISTOR

NETWORK

BUFFER

STRING

DAC

STRING

DAC

AD5302/AD5312/AD5322

INPUT

DAC

INTERFACE

LOGIC

SCLK

POWER-ON

RESET

REF

OUT

GNDV

REF

LDAC

DIN

00928-001

SYNC

BUFFER

Figure 1.

Summary of content (24 pages)

PAGE 1
2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs AD5302/AD5312/AD5322 FEATURES GENERAL DESCRIPTION AD5302: Two 8-bit buffered DACs in 1 package A version: ±1 LSB INL, B version: ±0.
PAGE 2
AD5302/AD5312/AD5322 TABLE OF CONTENTS Features .............................................................................................. 1 Low Power Serial Interface ....................................................... 15 Applications....................................................................................... 1 Double-Buffered Interface ........................................................ 15 General Description .....................................................................
PAGE 3
AD5302/AD5312/AD5322 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. Table 1.
PAGE 4
AD5302/AD5312/AD5322 2 Parameter POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V A Version 1 Min Typ Max Min 2.5 2.5 IDD (Full Power-Down) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V 5.5 B Version1 Typ Max Unit Test Conditions/Comments 5.
PAGE 5
AD5302/AD5312/AD5322 TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted. 1, 2, 3 Table 3. Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 Limit at TMIN, TMAX (A, B Version) 33 13 13 0 5 4.
PAGE 6
AD5302/AD5312/AD5322 GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE IDEAL ACTUAL POSITIVE OFFSET ERROR DAC CODE DEADBAND AMPLIFIER FOOTROOM (1mV) 02928-004 NEGATIVE OFFSET ERROR Figure 3. Transfer Function with Negative Offset GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE ACTUAL POSITIVE OFFSET ERROR DAC CODE Figure 4. Transfer Function with Positive Offset Rev.
PAGE 7
AD5302/AD5312/AD5322 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.1 Table 4. Parameter VDD to GND Digital Input Voltage to GND Reference Input Voltage to GND VOUTA, VOUTB to GND Operating Temperature Range Industrial (A, B Version) Storage Temperature Range Junction Temperature (TJ max) 10-Lead MSOP Power Dissipation θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) 1 Rating –0.3 V to +7 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.
PAGE 8
AD5302/AD5312/AD5322 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 2 VREF B 3 VREF A 4 VOUTA 5 AD5302/ AD5312/ AD5322 TOP VIEW (Not to Scale) 10 GND 9 DIN 8 SCLK 7 SYNC 6 VOUTB 00928-003 LDAC 1 Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic LDAC 2 3 VDD VREFB 4 VREFA 5 6 7 VOUTA VOUTB SYNC 8 SCLK 9 DIN 10 GND Description Active Low Control Input. This pin transfers the contents of the input registers to their respective DAC registers.
PAGE 9
AD5302/AD5312/AD5322 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSB, from a straight line passing through the actual endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 10
AD5302/AD5312/AD5322 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 0.2 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 0.1 0 –0.1 –0.5 0 50 100 150 200 –0.3 250 00928-009 –1.0 00928-006 –0.2 0 50 100 Figure 6. AD5302 Typical INL Plot 0.6 TA = 25°C VDD = 5V 2 0.4 1 0.2 0 –1 TA = 25°C VDD = 5V 0 –0.2 0 200 400 600 800 00928-010 –0.6 1000 0 200 CODE 400 600 800 1000 CODE Figure 7. AD5312 Typical INL Plot 3 250 –0.
PAGE 11
AD5302/AD5312/AD5322 1.00 TA = 25°C VDD = 5V 0.75 VDD = 5V VDD = 3V 0.25 FREQUENCY ERROR (LSB) 0.50 MAX INL MAX DNL 0 MIN DNL –0.25 MIN INL –1.00 00928-012 –0.75 2 3 4 00928-015 –0.50 0 100 5 150 VREF (V) 0.75 250 IDD (µA) 300 350 400 Figure 15. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 12. AD5302 INL and DNL Error vs. VREF 1.00 200 5 VDD = 5V VREF = 3V 5V SOURCE 4 MAX DNL MAX INL 0.25 0 –0.25 MIN INL –0.50 2 MIN DNL 3V SINK 5V SINK 00928-013 –1.
PAGE 12
AD5302/AD5312/AD5322 600 VDD = 5V TA = 25°C BOTH DACS IN GAIN-OF-TWO MODE REFERENCE INPUTS BUFFERED 500 CH2 400 +25°C –40°C IDD(µA) CLK 300 +105°C 200 VOUT CH1 00928-018 00928-021 100 0 2.5 3.0 3.5 4.0 4.5 5.0 CH1 1V, CH2 5V, TIME BASE = 5µs/DIV 5.5 VDD(V) Figure 18. Supply Current vs. Supply Voltage 1.0 Figure 21. Half-Scale Setting (¼ to ¾ Scale Code Change) TA = 25°C BOTH DACS IN THREE-STATE CONDITION VDD IDD (µA) 0.8 0.6 –40°C 0.4 +25°C CH1 VOUTA 0.2 3.2 3.7 4.
PAGE 13
AD5302/AD5312/AD5322 2.50 VOUT (V) 2mV/DIV 2.49 00928-024 00928-026 2.48 2.47 500ns/DIV 1µs/DIV Figure 26. DAC-to-DAC Crosstalk Figure 24. AD5322 Major-Code Transition 1.0 10 TA = 25°C VDD = 5V –10 dB –20 –30 –40 –60 10 00928-025 –50 100 1k 10k 100k 1M 0.5 0 –0.5 –1.0 10M 00928-027 FULL SCALE ERROR (V) 0 0 1 2 3 4 VREF (V) FREQUENCY(Hz) Figure 25. Multiplying Bandwidth (Small-Signal Frequency Response) Rev. D | Page 13 of 24 Figure 27. Full-Scale Error vs.
PAGE 14
AD5302/AD5312/AD5322 FUNCTIONAL DESCRIPTION DIGITAL-TO-ANALOG SECTION The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the DAC. Figure 28 shows a block diagram of the DAC architecture.
PAGE 15
AD5302/AD5312/AD5322 SERIAL INTERFACE The AD5302/AD5312/AD5322 are controlled over a versatile, 3-wire serial interface, which operates at clock rates up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. INPUT SHIFT REGISTER The input shift register is 16 bits wide (see Figure 30 to Figure 32). Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 2.
PAGE 16
AD5302/AD5312/AD5322 POWER-DOWN MODES The AD5302/AD5312/AD5322 have very low power consumption, dissipating only 0.7 mW with a 3 V supply and 1.5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into one of three power-down modes, which are selected by Bit 13 and Bit 12 (PD1 and PD0) of the control word. Table 7 shows how the state of the bits corresponds to the mode of operation of that particular DAC. Table 7.
PAGE 17
AD5302/AD5312/AD5322 MICROPROCESSOR INTERFACING AD5302/AD5312/AD5322 TO ADSP-2101/ADSP2103 INTERFACE AD5302/AD5312/AD5322 TO 80C51/80L51 INTERFACE Figure 34 shows a serial interface between the AD5302/AD5312/ AD5322 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP2103 should be set up to operate in the SPORT transmit alternate framing mode.
PAGE 18
AD5302/AD5312/AD5322 APPLICATIONS INFORMATION 6V to 16V TYPICAL APPLICATION CIRCUIT The AD5302/AD5312/AD5322 can be used with a wide range of reference voltages, especially if the reference inputs are configured to be unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0 V to VDD. More typically, the AD5302/AD5312/AD5322 can be used with a fixed, precision reference voltage.
PAGE 19
AD5302/AD5312/AD5322 OPTO-ISOLATED INTERFACE FOR PROCESS CONTROL APPLICATIONS Each AD5302/AD5312/AD5322 has a versatile 3-wire serial interface, making them ideal for generating accurate voltages in process control and industrial applications. Due to noise, safety requirements, or distance, it can be necessary to isolate the AD5302/AD5312/AD5322 from the controller. This can easily be achieved by using opto-isolators, which provide isolation in excess of 3 kV.
PAGE 20
AD5302/AD5312/AD5322 POWER SUPPLY BYPASSING AND GROUNDING COARSE AND FINE ADJUSTMENT USING THE AD5302/AD5312/AD5322 In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5302/AD5312/AD5322 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board.
PAGE 21
AD5302/AD5312/AD5322 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev. D | Page 21 of 24 0.70 0.55 0.40 091709-A 0.15 0.05 COPLANARITY 0.
PAGE 22
AD5302/AD5312/AD5322 ORDERING GUIDE Model 1, 2 AD5302ARM AD5302ARM-REEL7 AD5302ARMZ AD5302ARMZ-REEL AD5302ARMZ-REEL7 AD5302BRM AD5302BRM-REEL AD5302BRM-REEL7 AD5302BRMZ AD5302BRMZ-REEL AD5302BRMZ-REEL7 AD5312ARM AD5312ARMZ AD5312ARMZ-REEL7 AD5312BRM AD5312BRM-REEL AD5312BRM-REEL7 AD5312BRMZ AD5312BRMZ-REEL AD5312BRMZ-REEL7 AD5322ARM AD5322ARM-REEL7 AD5322ARMZ AD5322ARMZ-REEL7 AD5322BRM AD5322BRM-REEL AD5322BRM-REEL7 AD5322BRMZ AD5322BRMZ-REEL AD5322BRMZ-REEL7 AD5312WARMZ-REEL7 1 2 Temperature Range −40°C t
PAGE 23
AD5302/AD5312/AD5322 NOTES Rev.