Datasheet

AD5300
–4–
REV.
PIN CONFIGURATIONS
TOP VIEW
(Not to Scale)
6
5
4
1
2
3
V
OUT
GND
V
DD
SYNC
SCLK
DIN
AD5300
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
NC
AD5300
SYNC
V
OUT
GND
V
DD
SCLK
DIN
NC
NC = NO CONNECT
SOT-23
MSOP
PIN FUNCTION DESCRIPTIONS
SOT-23 MSOP
Pin No. Pin No. Mnemonic Function
14V
OUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
28GND Ground Reference Point for All Circuitry on the Part.
31V
DD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and V
DD
should be decoupled
to GND.
47DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
56SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates up to 30 MHz.
65SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the
input data. When SYNC goes low, it enables the input shift register and data is transferred in on the
falling edges of the following clocks. The DAC is updated following the 16th clock cycle, unless
SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and
the write sequence is ignored by the DAC.
NC 2, 3 NC No Connect.
D