Datasheet

AD5293
Rev. D | Page 21 of 24
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B terminal and wiper-to-A terminal that is proportional
to the input voltage at A to B, as shown in Figure 48. Unlike the
polarity of V
DD
to GND, which must be positive, voltage across
A to B, W to A, and W to B can be at either polarity.
07675-042
W
A
B
V
IN
V
OUT
Figure 48. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity,
connecting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B that
ranges from 0 V to 30 V − 1 LSB. Each LSB of voltage is equal to
the voltage applied across the A terminal and B terminal, divided
by the 1024 positions of the potentiometer divider. The general
equation defining the output voltage at V
W
, with respect to
ground for any valid input voltage applied to Terminal A and
Terminal B, is
B
A
W
V
D
V
D
DV ×
−
+×=
1024
1024
1024
)(
(3)
To optimize the wiper position update rate when in voltage
divider mode, it is recommended that the internal ±1% resistor
tolerance calibration feature be disabled by programming Bit C2
of the control register (see Table 11).
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
rheostat mode, the output voltage is dependent mainly on the ratio
of the internal resistors, R
WA
and R
WB
, and not on the absolute
values. Therefore, the temperature drift reduces to 5 ppm/°C.
EXT_CAP CAPACITOR
A 1 µF capacitor to GND must be connected to the EXT_CAP
pin (see Figure 49) on power-up and throughout the operation
of the AD5293. This capacitor must have a voltage rating of ≥7 V.
AD5293
GND
C1
1µF
EXT_CAP
07675-043
Figure 49. Hardware Setup for the EXT_CAP Pin
TERMINAL VOLTAGE OPERATING RANGE
The positive V
DD
and negative V
SS
power supplies of the AD5293
define the boundary conditions for proper 3-terminal, digital
potentiometer operation. Supply signals present on the A, B,
and W terminals that exceed V
DD
or V
SS
are clamped by the
internal forward-biased diodes (see Figure 50).
V
SS
V
DD
A
W
B
07675-044
Figure 50. Maximum Terminal Voltages Set by V
DD
and V
SS
The ground pin of the AD5293 is primarily used as a digital
ground reference. To minimize the digital ground bounce, the
AD5293 ground pin should be joined remotely to common ground.
The digital input control signals to the AD5293 must be referenced
to the device ground pin (GND) to satisfy the logic level defined
in the Specifications section.
Power-Up Sequence
Because there are diodes to limit the voltage compliance at the
A, B, and W terminals (see Figure 50), it is important to power
V
DD
and V
SS
first, before applying any voltage to the A, B, and W
terminals. Otherwise, the diode is forward-biased such that V
DD
and V
SS
are powered up unintentionally. The ideal power-up
sequence is GND, V
SS
, V
LOGIC
, V
DD
, the digital inputs, and then
V
A
, V
B
, and V
W
. The order of powering up V
A
, V
B
, V
W
, and the
digital inputs is not important, as long as they are powered after
V
DD
, V
SS
, and V
LOGIC
.
Regardless of the power-up sequence and the ramp rates of the
power supplies, the power-on preset activates after V
LOGIC
is
powered, restoring midscale to the RDAC register.