AD5293
Rev. D | Page 8 of 24
TIMING DIAGRAMS
t
4
t
3
t
2
t
5
t
7
t
6
D0D1
X
SYNC
SCLK
t
9
t
1
t
8
DIN
SDO
D6
D7
D2
XC3 C2
RDY
t
12
t
10
t
11
07675-003
RESET
t
RESET
Figure 3. Write Timing Diagram, CPOL = 0, CPHA =1
D0D1
X
SYNC
SCLK
t
9
t
14
t
13
t
11
DIN
SDO
X
D0
X
XC3
RDY
D0
X
X
C3
D0D1
C3
7675-004
Figure 4. Read Timing Diagram, CPOL = 0, CPHA =1
