Datasheet

AD5293
Rev. D | Page 7 of 24
INTERFACE TIMING SPECIFICATIONS
V
DD
= V
SS
= ±15 V, V
LOGIC
= 2.7 V to 5.5 V, and −40°C < T
A
< +105°C. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 5.
Parameter Limit
1
Unit Test Conditions/Comments
t
1
2
20 ns min SCLK cycle time
t
2
10 ns min SCLK high time
t
3
10 ns min SCLK low time
t
4
10 ns min
SYNC
to SCLK falling edge setup time
t
5
5 ns min Data setup time
t
6
5 ns min Data hold time
t
7
1 ns min
SCLK falling edge to SYNC
rising edge
t
8
400
3
ns min
Minimum SYNC
high time
t
9
14 ns min
SYNC
rising edge to next SCLK fall ignored
t
10
4
1 ns min
RDY rise to SYNC
falling edge
t
11
4
40 ns max
SYNC
rise to RDY fall time
t
12
4
2.4 μs max RDY low time, RDAC register write command execute time (resistor performance mode)
t
12
4
410 ns max RDY low time, RDAC register write command execute time (normal mode)
t
12
4
1.5 ms max Software\hardware reset
t
13
4
450 ns max RDY low time, RDAC register read command execute time
t
14
4
450 ns max SCLK rising edge to SDO valid
t
RESET
20 ns min
Minimum RESET
pulse width (asynchronous)
t
POWER-UP
5
2 ms max Power-on time to half scale
1
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency = 50 MHz.
3
Refer to t
12
and t
13
for RDAC register commands operations.
4
R
PULL_UP
= 2.2 kΩ to V
LOGIC
with a capacitance load of 168 pF.
5
Typical power supply voltage slew-rate of 2 V/ms.
DATA BITS
DB9 (MSB) DB0 (LSB)
D7 D6 D5 D4 D3
D2 D1
D0
CONTROL BITS
C0C1
C2
D9
D8
C3
00
07675-002
Figure 2. Shift Register Contents