Datasheet

AD5293
Rev. D | Page 19 of 24
RESET
A low-to-high transition of the hardware
RESET
pin loads the
RDAC register with midscale. The AD5293 can also be reset
through software by executing Command 3 (see ).
The control register is restored with default bits (see ).
Table 11
Table 13
RESISTOR PERFORMANCE MODE
This mode activates a new, patented 1% end-to-end resistor
tolerance that ensures a ±1% resistor tolerance on each code,
that is, code = half scale, R
WB
=10 kΩ ± 100 Ω. See Table 2 and
Tabl e 4 to verify which codes achieve ±1% resistor tolerance.
The resistor performance mode is activated by programming
Bit C2 of the control register (see Table 12 and Table 13). The
typical settling time is shown in Figure 32.
SDO PIN AND DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can
be used to read the contents of the wiper setting and control
register using Command 2, and Command 5, respectively (see
Tabl e 11) or the SDO pin can be used in daisy-chain mode.
Data is clocked out of SDO on the rising edge of SCLK. The
SDO pin contains an open-drain N-channel FET that requires
a pull-up resistor if this pin is used. To place the pin in high
impedance and minimize the power dissipation when the pin
is used, the 0x8001 data word followed by Command 0 should
be sent to the part. Table 10 provides a sample listing for the
sequence of the serial data input (DIN). Daisy chaining mini-
mizes the number of port pins required from the controlling IC.
As shown in Figure 45, users need to tie the SDO pin of one
package to the DIN pin of the next package. Users may need to
increase the clock period, because the pull-up resistor and the
capacitive loading at the SDO-to-DIN interface may require
additional time delay between subsequent devices.
When two AD5293s are daisy-chained, 32 bits of data are required.
The first 16 bits go to U2, and the second 16 bits go to U1. The
SYNC
pin should be held low until all 32 bits are clocked into
their respective serial registers. The
SYNC
pin is then pulled
high to complete the operation.
Keep the
SYNC
pin low until all 32 bits are clocked into their
respective serial registers. The
SYNC
pin is then pulled high to
complete the operation.
DIN SDO
SCLK SCLK
R
P
2.2k
DIN SDO
U1 U2
AD5293 AD5293
SYNC
V
LOGIC
MICRO-
CONTROLLER
SCLK SS
MOSI
SYNC
07675-039
Figure 45. Daisy-Chain Configuration Using SDO
Table 10. Minimize Power Dissipation at the SDO Pin
DIN SDO
1
Action
0xXXXX 0xXXXX Last user command sent to the digipot
0x8001 0xXXXX Prepares the SDO pin to be placed in high impedance mode
0x0000 High impedance The SDO pin is placed in high impedance
1
X = don’t care.
Table 11. Command Operation Truth Table
Command Bits[B13:B10] Data Bits[B9:B0]
1
Command
C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Operation
0 0 0 0 0 X X X X X X X X X X NOP command. Do nothing.
1 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register data
to RDAC.
2 0 0 1 0 X X X X X X X X X X Read RDAC wiper setting from SDO
output in the next frame.
3 0 1 0 0 X X X X X X X X X X Reset. Refresh RDAC with midscale code.
4 0 1 1 0 X X X X X X X D2 D1 X Write contents of serial register data
to control register.
5 0 1 1 1 X X X X X X X X X X Read control register from SDO output
in the next frame.
6 1 0 0 0 X X X X X X X X X D0 Software power-down.
D0 = 0 (normal mode).
D0 = 1 (device placed in shutdown
mode).
1
X = don’t care.
Table 12. Control Register Bit Map
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
1
X
1
X
1
X
1
X
1
X
1
X
1
C2 C1 X
1
1
X = don’t care.