Datasheet

AD5291/AD5292
Rev. D | Page 27 of 32
Operation of the digital potentiometer in the voltage divider
mode results in a more accurate operation over temperature.
Unlike the rheostat mode, the output voltage is dependent
mainly on the ratio of the internal resistors, R
WA
and R
WB
, and
not the absolute values. Therefore, the temperature drift reduces
to 5 ppm/°C.
The ground pins of the AD5291 and AD5292 devices are
primarily used as a digital ground reference. To minimize the
digital ground bounce, the AD5291 and AD5292 ground
terminals should be joined remotely to the common ground.
The digital input control signals to the AD5291 and AD5292
must be referenced to the device ground pin (GND), and satisfy
the logic level defined in the Specifications section.
EXT_CAP CAPACITOR
Power-Up Sequence
A 1 µF capacitor to GND must be connected to the EXT_CAP
pin (see Figure 68) on power-up and throughout the operation
of the AD5291 and AD5292.
To ensure that the AD5291 and AD5292 power up correctly, a
1 µF capacitor must be connected to the EXT_CAP pin. Because
there are diodes to limit the voltage compliance at Terminal A,
Terminal B, and Terminal W (see Figure 69), it is important to
power V
DD
and V
SS
first before applying any voltage to Terminal A,
Terminal B, and Terminal W. Otherwise, the diode is forward-
biased such that V
DD
and V
SS
are powered up unintentionally.
The ideal power-up sequence is GND, V
SS
, V
LOGIC
and V
DD
, the
digital inputs, and then V
A
, V
B
, and V
W
. The order of powering
up V
A
, V
B
, V
W
, and the digital inputs is not important as long as
they are powered after V
DD
, V
SS
, and V
LOGIC
.
AD5291/
AD5292
GND
C1
1µF
OTP
MEMORY
BLOCK
07674-054
EXT_CAP
Figure 68. Hardware Setup for EXT_CAP Pin
TERMINAL VOLTAGE OPERATING RANGE
Regardless of the power-up sequence and the ramp rates of the
power supplies, after V
LOGIC
is powered, the power-on preset
activates, restoring the 20-TP memory value to the RDAC register.
The positive V
DD
and negative V
SS
power supplies of the
AD5291 and AD5292 define the boundary conditions for
proper 3-terminal digital potentiometer operation. Supply
signals present on Terminal A, Terminal B, and Terminal W
that exceed V
DD
or V
SS
are clamped by the internal forward-
biased diodes (see Figure 69).
V
SS
V
DD
A
W
B
07674-055
Figure 69. Maximum Terminal Voltages Set by V
DD
and V
SS