Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Test Circuits
- Theory of Operation
- Serial Data Interface
- Shift Register
- RDAC Register
- 20-TP Memory
- Write Protection
- Basic Operation
- 20-TP Readback and Spare Memory Status
- Shutdown Mode
- Resistor Performance Mode
- Reset
- SDO Pin and Daisy-Chain Operation
- RDAC Architecture
- Programming the Variable Resistor
- Programming the Potentiometer Divider
- EXT_CAP Capacitor
- Terminal Voltage Operating Range
- Applications Information
- Outline Dimensions
Data Sheet AD5291/AD5292
APPLICATIONS INFORMATION
analog.com Rev. G | 30 of 33
HIGH VOLTAGE DAC
The AD5292 can be configured as a high voltage DAC, with output
voltage as high as 33 V. The circuit is shown in Figure 70. The
output is
V
OUT
D =
D
1024
×
1 . 2 V × 1 +
R
2
R
1
(7)
where D is the decimal code from 0 to 1023.
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AD5292
U2
AD8512
V+
V–
AD8512
V
OUT
V
DD
U1B
V
DD
R
BIAS
ADR512
D1
R
2
R
1
B
20kΩ
U1A
Figure 70. High Voltage DAC
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
For applications that require high current adjustments such as a
laser diode or tunable laser, a boosted voltage source can be
considered; see Figure 71.
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W
SIGNAL
C
C
R
BIAS
LD
V
IN
A
B
V
OUT
U1
AD5292
U3 2N7002
U2
I
L
OP184
Figure 71. Programmable Boosted Voltage Source
In this circuit, the inverting input of the op amp forces V
OUT
to be
equal to the wiper voltage set by the digital potentiometer. The load
current is then delivered by the supply via the N-channel FET (U3).
The N-Channel FET power handling must be adequate to dissipate
(V
IN
− V
OUT
) × I
L
power. This circuit can source a maximum of 100
mA with a 33 V supply.
HIGH ACCURACY DAC
It is possible to configure the AD5292 as a high accuracy DAC
by optimizing the resolution of the device over a specific reduced
voltage range. This is achieved by placing external resistors on
either side of the RDAC, as shown in Figure 72. The improved
±1% R-Tolerance specification greatly reduces error associated
with matching to discrete resistors.
V
OUT
(D) =
R
3
+ (
D
1024
× R
AB
) × V
DD
R
1
+ (
(1024 − D)
1024
) × R
AB
+ R
3
(8)
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AD5292
U1
V
OUT
B
R
2
20kΩ
R
1
R
3
±1%
OP1177
V+
V–
V
DD
V
DD
U2
Figure 72. Optimizing Resolution
VARIABLE GAIN INSTRUMENTATION
AMPLIFIER
The AD8221 in conjunction with the AD5291/AD5292 and the
ADG1207, as shown in Figure 73, make an excellent instrumenta-
tion amplifier for use in data acquisition systems. The data acquis-
ition system’s low distortion and low noise enable it to condition
signals in front of a variety of ADCs.
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AD8221
AD5292
+V
IN1
V
DD
V
OUT
V
SS
ADG1207
+V
IN4
–V
IN1
–V
IN4
Figure 73. Data Acquisition System
The gain can be calculated by using Equation 9.
G(D) = 1 +
49.4 kΩ
D/1024 × R
AB
(9)
AUDIO VOLUME CONTROL
The excellent THD performance and high voltage capability make
the AD5291/AD5292 ideal for a digital volume control as an audio
attenuator or gain amplifier. A typical problem in these systems
is that a large step change in the volume level at any arbitrary
time can lead to an abrupt discontinuity of the audio signal causing
an audible zipper noise. To prevent this, a zero-crossing window
detector can be inserted to the SYNC line to delay the device
update until the audio signal crosses the window. Because the input
signal can operate on top of any dc level rather than absolute zero
volt level, zero-crossing in this case means the signal is ac-coupled,
and the dc offset level is the signal zero reference point.
The configuration to reduce zipper noise is shown in Figure 74,
and the results of using this configuration is shown in Figure 75.
The input is ac-coupled by C1 and attenuated down before feeding
into the window comparator formed by U2, U3, and U4B. U6 is
used to establish the signal zero reference. The upper limit of the
comparator is set above its offset and, therefore, the output pulses
high whenever the input falls between 2.502 V and 2.497 V (or
0.005 V window) in this example. This output is AND’ed with the
SYNC signal such that the AD5291/AD5292 updates whenever
the signal crosses the window. To avoid a constant update of the
device, the SYNC signal should be programmed as two pulses,
rather than as one.