Datasheet

Data Sheet AD5291/AD5292
THEORY OF OPERATION
analog.com Rev. G | 29 of 33
equations defining the output voltage at V
W
with respect to ground
for any valid input voltage applied to Terminal A and Terminal B are
AD5291:V
W
D =
D
256
× V
A
+
256 − D
256
× V
B
(5)
AD5292:V
W
D =
D
1024
× V
A
+
1024 − D
1024
× V
B
(6)
If using the AD5291/AD5292 in voltage divider mode as shown
in Figure 67, then the ±1% resistor tolerance calibration feature
reduces the error when matching with discrete resistors. However,
it is recommended to disable the internal ±1% resistor tolerance
calibration feature by programming Bit C2 of the control register
(see Table 12 and Table 13) to optimize wiper position update rate.
In this configuration, the RDAC is ratiometric and resistor tolerance
error does not affect performance.
Operation of the digital potentiometer in the voltage divider mode
results in a more accurate operation over temperature. Unlike the
rheostat mode, the output voltage is dependent mainly on the ratio
of the internal resistors, R
WA
and R
WB
, and not the absolute values.
Therefore, the temperature drift reduces to 5 ppm/°C.
EXT_CAP CAPACITOR
A 1 µF capacitor to GND must be connected to the EXT_CAP pin
(see Figure 68) on power-up and throughout the operation of the
AD5291/AD5292.
AD5291/
AD5292
GND
C1
1µF
OTP
MEMORY
BLOCK
07674-054
EXT_CAP
Figure 68. Hardware Setup for EXT_CAP Pin
TERMINAL VOLTAGE OPERATING RANGE
The positive V
DD
and negative V
SS
power supplies of the AD5291/
AD5292 define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminal A,
Terminal B, and Terminal W that exceed V
DD
or V
SS
are clamped by
the internal forward-biased diodes (see Figure 69).
V
SS
V
DD
A
W
B
07674-055
Figure 69. Maximum Terminal Voltages Set by V
DD
and V
SS
The ground pins of the AD5291/AD5292 devices are primarily
used as a digital ground reference. To minimize the digital ground
bounce, the AD5291/AD5292 ground terminals should be joined
remotely to the common ground. The digital input control signals
to the AD5291/AD5292 must be referenced to the device ground
pin (GND), and satisfy the logic level defined in the Specifications
section.
Power-Up Sequence
To ensure that the AD5291/AD5292 power up correctly, a 1 µF
capacitor must be connected to the EXT_CAP pin. Because there
are diodes to limit the voltage compliance at Terminal A, Terminal
B, and Terminal W (see Figure 69), it is important to power V
DD
and V
SS
first before applying any voltage to Terminal A, Terminal B,
and Terminal W. Otherwise, the diode is forward-biased such that
V
DD
and V
SS
are powered up unintentionally. The ideal power-up
sequence is GND, V
SS
, V
LOGIC
and V
DD
, the digital inputs, and then
V
A
, V
B
, and V
W
. The order of powering up V
A
, V
B
, V
W
, and the
digital inputs is not important as long as they are powered after
V
DD
, V
SS
, and V
LOGIC
.
Regardless of the power-up sequence and the ramp rates of the
power supplies, after V
LOGIC
is powered, the power-on preset
activates, restoring the 20-TP memory value to the RDAC register.