Datasheet

Data Sheet AD5291/AD5292
THEORY OF OPERATION
analog.com Rev. G | 28 of 33
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices has patented the
RDAC segmentation architecture for all the digital potentiometers.
In particular, the AD5291/AD5292 employ a three-stage segmenta-
tion approach, as shown in Figure 65. The AD5291/AD5292 wiper
switches are designed with the transmission gate CMOS topology
and with the gate voltages derived from V
DD
and V
SS
.
R
W
S
W
W
R
W
8-/10-BIT
ADDRESS
DECODER
A
R
L
R
L
R
M
R
M
B
R
M
R
M
R
L
R
L
07674-051
Figure 65. Simplified RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—1% Resistor Tolerance
The AD5291/AD5292 operate in rheostat mode when only two
terminals are used as a variable resistor. The unused terminal can
be left floating or tied to the W terminal, as shown in Figure 66.
W
A
B
W
A
B
W
A
B
07674-052
Figure 66. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B, R
AB
, is
available in 20 kΩ, 50 kΩ, and 100 kΩ, and 256 or 1024 tap points
accessed by the wiper terminal. The 8-/10-bit data in the RDAC
latch is decoded to select one of the 256/1024 possible wiper
settings. The AD5291/AD5292 contain an internal ±1% resistor
performance mode that can be disabled or enabled (this is enabled
by default), by programming Bit C2 of the control register (see
Table 12 and Table 13). The digitally programmed output resistance
between the W terminal and the A terminal, R
WA
, and between
the W terminal and B terminal, R
WB
, is internally calibrated to
give a maximum of ±1% absolute resistance error across a wide
code range. As a result, the general equations for determining the
digitally programmed output resistance between the W terminal and
B terminal are
AD5291:R
WB
D =
D
256
× R
AB
(1)
AD5292:R
WB
D =
D
1024
× R
AB
(2)
where:
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
R
AB
is the end-to-end resistance.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the W terminal and the A terminal also produces
a digitally controlled complementary resistance, R
WA
. R
WA
is also
calibrated to give a maximum of 1% absolute resistance error.
R
WA
starts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equations for this
operation are
AD5291:R
WA
D =
256 − D
256
× R
AB
(3)
AD5292:R
WA
D =
1024 − D
1024
× R
AB
(4)
where:
D is the decimal equivalent of the binary code loaded in the 8-/
10‑bit RDAC register.
R
AB
is the end-to-end resistance.
In the zero-scale condition, a finite total wiper resistance of 60 Ω
is present. Regardless of which setting the part is operating in,
take care to limit the current between Terminal A and Terminal B,
between Terminal W and Terminal A, and between Terminal W and
Terminal B, to the maximum continuous current of ±3 mA or to
the pulse current specified in Table 8. Otherwise, degradation or
possible destruction of the internal resistors may occur.
PROGRAMMING THE POTENTIOMETER
DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at the
wiper to B and at the wiper to A that is proportional to the input
voltage at A to B, as shown in Figure 67. Unlike the polarity of V
DD
to GND, which must be positive, voltage across A to B, W to A, and
W to B can be at either polarity.
W
A
B
V
IN
V
OUT
07674-053
Figure 67. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity, connect-
ing the A terminal to 30 V and the B terminal to ground produces
an output voltage at the Wiper W to Terminal B ranging from 0
V to 1 LSB less than 30 V. Each LSB of voltage is equal to
the voltage applied across Terminal A and Terminal B, divided by
the 256/1024 positions of the potentiometer divider. The general