Datasheet

Data Sheet AD5291/AD5292
THEORY OF OPERATION
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The AD5291/AD5292 digital potentiometers are designed to oper-
ate as true variable resistors for analog signals that remain within
the terminal voltage range of VSS < VTERM < VDD. The patented
±1% resistor tolerance feature helps to minimize the total RDAC
resistance error, which reduces the overall system error by offering
better absolute matching and improved open-loop performance.
The digital potentiometer wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratchpad regis-
ter, allowing as many value changes as necessary to place the
potentiometer wiper in the correct position. The RDAC register
can be programmed with any position setting using the standard
SPI interface by loading the 16-bit data-word. Once a desirable
position is found, this value can be stored in a 20-TP memory
register. Thereafter, the wiper position is always restored to that
position for subsequent power-up. The storing of 20-TP data takes
approximately 6 ms; during this time, the shift register is locked,
preventing any changes from taking place. The RDY pin identifies
the completion of this 20-TP storage.
SERIAL DATA INTERFACE
The AD5291/AD5292 contain a serial interface (SYNC, SCLK, DIN
and SDO) that is compatible with SPI interface standards, as
well as most DSPs. The part allows writing of data via the serial
interface to every register.
SHIFT REGISTER
The AD5291/AD5292 shift register is 16 bits wide (see Figure 2).
The 16-bit input word consists of two zeros, followed by four control
bits, and 10 RDAC data bits. For the AD5291, the lower two RDAC
data bits are don’t cares if the RDAC register is read from or
written to. Data is loaded MSB first (Bit DB15). The four control bits
determine the function of the software command (see Table 11).
Figure 3 shows a timing diagram of a typical AD5291 and AD5292
write sequence.
The write sequence begins by bringing the SYNC line low. The
SYNC pin must be held low until the complete data-word is loaded
from the DIN pin. When SYNC returns high, the serial data-word
is decoded according to the commands in Table 11. The command
bits (Cx) control the operation of the digital potentiometer. The
data bits (Dx) are the values that are loaded into the decoded
register. The AD5291/AD5292 have an internal counter that counts
a multiple of 16 bits (a frame) for proper operation. For example,
AD5291/AD5292 work with a 32-bit word but does not work proper-
ly with a 31-bit or 33-bit word. The AD5291/AD5292 do not require
a continuous SCLK, when SYNC is high, and all serial interface
pins should be operated at close to the VLOGIC supply rails to
minimize power consumption in the digital input buffers.
Table 11. Command Operation Truth Table
Command DB15 DB14
Command
Bits[DB13:DB10] Data Bits[DB9:DB0]
1
OperationC3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 X X X X X X X X X X NOP command: do nothing.
1 0 0 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D1
2
D0
2
Write contents of serial data to RDAC.
2 0 0 0 0 1 0 X X X X X X X X X X Read RDAC wiper setting from the
SDO output in the next frame.
3 0 0 0 0 1 1 X X X X X X X X X X Store wiper setting: store RDAC
setting to 20-TP memory.
4 0 0 0 1 0 0 X X X X X X X X X X Reset: refresh RDAC with 20-TP
stored value.
5 0 0 0 1 0 1 X X X X X D4 D3 D2 D1 D0 Read contents of 20-TP memory, or
status of 20-TP memory, from the SDO
output in the next frame.
6 0 0 0 1 1 0 X X X X X X D3 D2 D1 D0 Write contents of serial data to control
register.
7 0 0 0 1 1 1 X X X X X X X X X X Read control register from the SDO
output in the next frame.
8 0 0 1 0 0 0 X X X X X X X X X D0 Software shutdown.
D0 = 0 (normal mode).
D0 = 1 (device placed in shutdown
mode).
1
X = don’t care.
2
In the AD5291, this bit is a don’t care.