Datasheet

AD5290 Data Sheet
Rev. C | Page 10 of 20
PIN CONFIGURATION AND DESCRIPTIONS
04716-004
A
1
B
2
V
SS
3
GND
4
CS
5
W
10
V
DD
9
SDO
8
SDI
7
CLK
6
AD5290
TOP VIEW
(Not to Scale)
Figure 4. AD5290 Pin Configuration
Table 6. AD5290 Pin Function Descriptions
Pin No. Mnemonic Description
1 A A Terminal. V
SS
≤ V
A
≤ V
DD
.
2 B B Terminal. V
SS
≤ V
B
≤ V
DD
.
3 V
SS
Negative Supply. Connect to 0 V for single-supply applications.
4 GND Digital Ground.
5
CS
Chip Select Input; Active Low. When
CS
returns high, data is loaded into the wiper register.
6 CLK Serial Clock Input. Positive edge triggered.
7 SDI Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
8 SDO
Serial Data Output Pin. Internal N-Ch FET with open-drain output that requires external pull-up resistor.
It shifts out the previous eight SDI bits that allow daisy-chain operation of multiple packages.
9
V
DD
Positive Power Supply.
10 W W Terminal. V
SS
≤ V
W
≤ V
DD
.