Datasheet

Data Sheet AD5290
Rev. C | Page 7 of 20
INTERFACE TIMING CHARACTERISTICS
Table 3.
Parameter
1, 2
Symbol Conditions Min Typ Max Unit
Clock Frequency f
CLK
4 MHz
Input Clock Pulse Width t
CH
, t
CL
Clock level high or low 120 ns
Data Setup Time t
DS
30 ns
Data Hold Time t
DH
20 ns
CLK to SDO Propagation Delay
3
t
PD
R
Pull-up
= 2.2 kΩ, C
L
< 20 pF 10 100 ns
CS Setup Time
t
CSS
120 ns
CS High Pulse Width
t
CSW
150
ns
CLK Fall to CS Fall Hold Time
t
CSH0
10 ns
CLK Rise to CS Rise Hold Time
t
CSH
120 ns
CS Rise to Clock Rise Setup
t
CS1
120 ns
1
See Figure 3 for the location of the measured values. All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of
1.6 V. Switching characteristics are measured using V
DD
= +15 V and V
SS
= −15 V.
2
Guaranteed by design and not subject to production test.
3
Propagation delay depends on the value of V
DD
, R
Pull-up
, and C
L
.