Datasheet

AD5280/AD5282
Rev. C | Page 4 of 28
Parameter Symbol Conditions Min Typ
1
Max Unit
Total Harmonic Distortion THD
W
V
A
= 1 V rms, R
AB
= 20 kΩ 0.014 %
V
B
= 0 V dc, f = 1 kHz
V
W
Settling Time t
S
V
A
= 5 V, V
B
= 5 V, ±1 LSB error band 5 μs
Crosstalk CT
V
A
= V
DD
, V
B
= 0 V, measure V
W1
with
adjacent RDAC making full-scale
code change
15 nV-s
Analog Crosstalk CTA
Measure V
W1
with V
W2
= 5 V p-p @ f =
10 kHz
−62 dB
Resistor Noise Voltage e
N_WB
R
WB
= 20 kΩ, f = 1 kHz 18 nV/√Hz
INTERFACE TIMING CHARACTERISTICS (applies to all parts)
6, 10, 11
SCL Clock Frequency f
SCL
0
400 kHz
t
BUF
Bus Free Time Between
Stop and Start
t
1
1.3 μs
t
HD:STA
Hold Time (Repeated
Start)
t
2
After this period, the first clock pulse
is generated
0.6
μs
t
LOW
Low Period of SCL Clock t
3
1.3 μs
t
HIGH
High Period of SCL Clock t
4
0.6 μs
t
SU:STA
Setup Time for Start
Condition
t
5
0.6 μs
t
HD:DAT
Data Hold Time t
6
0
0.9 μs
t
SU:DAT
Data Setup Time t
7
100 ns
t
F
Fall Time of Both SDA and
SCL Signals
t
8
300 ns
t
R
Rise Time of Both SDA and
SCL Signals
t
9
300 ns
t
SU:STO
Setup Time for STOP
Condition
t
10
0.6 μs
02929-042
1
Typicals represent average readings at 25°C, V
DD
= +5 V, V
SS
= −5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use V
DD
= 5 V.
10
See timing diagram (Figure 3) for location of measured values.
11
Standard I
2
C mode operation is guaranteed by design.
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
PS S
SCL
SDA
P
Figure 3. Detailed Timing Diagram