Datasheet

Data Sheet AD5272/AD5274
Rev. D | Page 7 of 28
INTERFACE TIMING SPECIFICATIONS
V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 7.
Limit at T
MIN
, T
MAX
Parameter Conditions
1
Min Max Unit Description
f
SCL
2
Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz Serial clock frequency
t
1
Standard mode 4 µs t
HIGH
, SCL high time
Fast mode
0.6
µs
t
HIGH
, SCL high time
t
2
Standard mode 4.7 µs t
LOW
, SCL low time
Fast mode 1.3 µs t
LOW
, SCL low time
t
3
Standard mode 250 ns t
SU;DAT
, data setup time
Fast mode 100 ns t
SU;DAT
, data setup time
t
4
Standard mode 0 3.45 µs t
HD ;DAT
, data hold time
Fast mode 0 0.9 µs t
HD ;DAT
, data hold time
t
5
Standard mode 4.7 µs t
SU;STA
, set-up time for a repeated start condition
Fast mode 0.6 µs t
SU;STA
, set-up time for a repeated start condition
t
6
Standard mode 4 µs t
HD;STA
, hold time (repeated) start condition
Fast mode 0.6 µs t
HD;STA
, hold time (repeated) start condition
High speed mode 160 ns t
HD;STA
, hold time (repeated) start condition
t
7
Standard mode 4.7 µs t
BUF
, bus free time between a stop and a start condition
Fast mode 1.3 µs t
BUF
, bus free time between a stop and a start condition
t
8
Standard mode 4 µs t
SU;STO
, setup time for a stop condition
Fast mode 0.6 µs t
SU;STO
, setup time for a stop condition
t
9
Standard mode 1000 ns t
RDA
, rise time of SDA signal
Fast mode
300
ns
t
RDA
, rise time of SDA signal
t
10
Standard mode 300 ns t
FDA
, fall time of SDA signal
Fast mode 300 ns t
FDA
, fall time of SDA signal
t
11
Standard mode 1000 ns t
RCL
, rise time of SCL signal
Fast mode 300 ns t
RCL
, rise time of SCL signal
t
11A
Standard mode
1000
ns
t
RCL1
, rise time of SCL signal after a repeated start condition and
after an acknowledge bit
Fast mode 300 ns t
RCL1
, rise time of SCL signal after a repeated start condition and
after an acknowledge bit
t
12
Standard mode 300 ns t
FCL
, fall time of SCL signal
Fast mode 300 ns t
FCL
, fall time of SCL signal
t
13
RESET
pulse time
20
ns
Minimum
RESET
low time
t
SP
3
Fast mode 0 50 ns Pulse width of spike suppressed
t
EXEC
4, 5
500 ns Command execute time
t
RDAC_R-PERF
2 µs RDAC register write command execute time (R-Perf mode)
t
RDAC_NORMAL
600 ns RDAC register write command execute time (normal mode)
t
MEMORY_READ
6 µs Memory readback execute time
t
MEMORY_PROGRAM
350
ms
Memory program time
t
RESET
600 µs Reset 50-TP restore time
t
POWER-UP
6
2 ms Power-on 50-TP restore time
1
Maximum bus capacitance is limited to 400 pF.
2
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
3
Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.
4
Refer to t
RDAC_R-PERF
and t
RDAC_NORMAL
for RDAC register write operations.
5
Refer to t
MEMORY_READ
and
t
MEMORY_PROGRAM
for memory commands operations.
6
Maximum time after V
DD
− V
SS
is equal to 2.5 V.