Datasheet

AD5272/AD5274 Data Sheet
Rev. D | Page 10 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
DD
1
V
SS
2
A
3
W
4
10
9
8
SCL
ADDR
7
5
EXT_CAP
SDA
6
GND
AD5272/
AD5274
TOP VIEW
(Not to Scale)
RESET
08076-004
Figure 4. MSOP Pin Configuration
ADDR
V
DD
1
V
SS
2
A
3
W
4
RESET
10
9
8
SCL
7
5
EXT_CAP
SDA
6
GND
NOTES
1. THE EXPOSED PAD IS LEFT FLOATING
OR IS TIED TO V
SS
.
AD5272/
AD5274
(EXPOSED
PAD)
08076-040
Figure 5. LFCSP Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
DD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
2 A Terminal A of RDAC. V
SS
≤ V
A
≤ V
DD
.
3 W Wiper terminal of RDAC. V
SS
≤ V
W
≤ V
DD
.
4 V
SS
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 F ceramic capacitors
and 10 F capacitors.
5 EXT_CAP
External Capacitor. Connect a 1 µF capacitor between EXT_CAP and V
SS
. This capacitor must have a voltage
rating of ≥7 V.
6 GND Ground Pin, Logic Ground Reference.
7
RESET
Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory
default loads midscale until the first 50-TP wiper memory location is programmed. RESET
is active low. Tie RESET
to V
DD
if not used.
8 SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input registers. It is
a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
9 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input registers.
10 ADDR Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 11).
EPAD
Exposed Pad
(LFCSP Only)
Leave floating or tie to V
SS
.