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1024-/256-Position, 1% Resistor Tolerance Error,

C Interface and 50-TP Memory Digital Rheostat

Data Sheet

AD5272/AD5274

Rev. D Document Feedback

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FEATURES

Single-channel, 1024-/256-position resolution

20 kΩ, 50 kΩ, 100 kΩ nominal resistance

Maximum ±1% nominal resistor tolerance error

50-times programmable (50-TP) wiper memory

Rheostat mode temperature coefficient: 5 ppm/°C

2.7 V to 5.5 V single-supply operation

±2.5 V to ±2.75 V dual-supply operation for ac or bipolar

operations

C-compatible interface

Wiper setting readback

Power on refreshed from 50-TP memory

Thin LFCSP 10-lead, 3 mm × 3 mm × 0.8 mm package

Compact MSOP, 10-lead 3 mm × 4.9 mm × 1.1 mm package

APPLICATIONS

Mechanical rheostat replacements

Op-amp: variable gain control

Instrumentation: gain, offset adjustment

Programmable voltage to current conversions

Programmable filters, delays, time constants

Programmable power supply

Sensor calibration

FUNCTIONAL BLOCK DIAGRAM

10/8

AD5272/AD5274

SCL

ADDR

SDA

SERIAL

INTERFACE

POWER-ON

RESET

RDAC

50-TP

MEMORY

BLOCK

RESET

EXT_CAP GND

08076-001

Figure 1.

GENERAL DESCRIPTION

The AD5272/AD5274

are single-channel, 1024-/256-position

digital rheostats that combine industry leading variable resistor

performance with nonvolatile memory (NVM) in a compact

package.

The AD5272/AD5274 ensure less than 1% end-to-end resistor

tolerance error and offer 50-times programmable (50-TP) memory.

The guaranteed industry leading low resistor tolerance error

feature simplifies open-loop applications as well as precision

calibration and tolerance matching applications.

The AD5272/AD5274 device wiper settings are controllable

through the I

C-compatible digital interface. Unlimited

adjustments are allowed before programming the resistance

value into the 50-TP memory. The AD5272/AD5274 do not

require any external voltage supply to facilitate fuse blow and

there are 50 opportunities for permanent programming. During

50-TP activation, a permanent blow fuse command freezes the

wiper position (analogous to placing epoxy on a mechanical

trimmer).

The AD5272/AD5274 are available in a 3 mm × 3 mm 10-lead

LFCSP package and in a 10-lead MSOP package. The parts are

guaranteed to operate over the extended industrial temperature

range of −40°C to +125°C.

Protected by U.S. Patent Number 7688240.

Summary of content (28 pages)

PAGE 1
024-/256-Position, 1% Resistor Tolerance Error, I2C Interface and 50-TP Memory Digital Rheostat AD5272/AD5274 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD POWER-ON RESET RDAC REGISTER SCL SDA I2C SERIAL INTERFACE A 10/8 W 50-TP MEMORY BLOCK ADDR RESET VSS APPLICATIONS AD5272/AD5274 EXT_CAP GND 08076-001 Single-channel, 1024-/256-position resolution 20 kΩ, 50 kΩ, 100 kΩ nominal resistance Maximum ±1% nominal resistor tolerance error 50-times programmable (50-TP) wiper memory Rheostat m
PAGE 2
AD5272/AD5274 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Shift Register ............................................................................... 18 Applications ....................................................................................... 1 Write Operation.......................................................................... 19 Functional Block Diagram ......................................
PAGE 3
Data Sheet AD5272/AD5274 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5272 VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted. Table 1.
PAGE 4
AD5272/AD5274 Parameter Power Supply Rejection Ratio5 DYNAMIC CHARACTERISTICS5, 11 Bandwidth Total Harmonic Distortion Resistor Noise Density Data Sheet Symbol PSRR Test Conditions/Comments ΔVDD/ΔVSS = ±5 V ± 10% RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Min −3 dB, RAW = 10 kΩ, Terminal W, see Figure 41 RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ VA = 1 V rms, f = 1 kHz, code = half scale RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Typ 1 Ma
PAGE 5
Data Sheet AD5272/AD5274 ELECTRICAL CHARACTERISTICS—AD5274 VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted. Table 4.
PAGE 6
AD5272/AD5274 Parameter DYNAMIC CHARACTERISTICS5, 11 Bandwidth Total Harmonic Distortion Resistor Noise Density Data Sheet Symbol Test Conditions/Comments Min −3 dB, RAW = 10 kΩ, Terminal W, see Figure 41 RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ VA = 1 V rms, f = 1 kHz, code = half scale RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Typ 1 Max Unit kHz 300 120 60 dB −90 −88 −85 nV/√Hz 13 25 32 Typical specifications represent average
PAGE 7
Data Sheet AD5272/AD5274 INTERFACE TIMING SPECIFICATIONS VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7.
PAGE 8
AD5272/AD5274 Data Sheet Shift Register and Timing Diagrams DB9 (MSB) C3 0 C1 C2 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 08076-003 0 DB0 (LSB) DATA BITS CONTROL BITS Figure 2. Shift Register Content t11 t12 t6 t8 t2 SCL t5 t1 t6 t4 t10 t3 t9 SDA t7 P S S P 08076-002 RESET t13 Figure 3. 2-Wire Serial Interface Timing Diagram Rev.
PAGE 9
Data Sheet AD5272/AD5274 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 8. Parameter VDD to GND VSS to GND VDD to VSS VA, VW to GND Digital Input and Output Voltage to GND EXT_CAP to VSS IA, IW Continuous RAW = 20 kΩ RAW = 50 kΩ, 100 kΩ Pulsed 1 Frequency > 10 kHz Frequency ≤ 10 kHz Operating Temperature Range 4 Maximum Junction Temperature (TJ Maximum) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Rating –0.3 V to +7.
PAGE 10
AD5272/AD5274 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 10 ADDR AD5272/ AD5274 9 SCL W 3 VSS 4 (EXPOSED PAD) 7 RESET A 2 A 2 W 3 VSS 4 10 ADDR AD5272/ AD5274 9 SCL 8 SDA TOP VIEW (Not to Scale) 7 RESET 6 GND EXT_CAP 5 EXT_CAP 5 6 GND NOTES 1. THE EXPOSED PAD IS LEFT FLOATING OR IS TIED TO VSS. 08076-004 VDD 1 8 SDA Figure 4. MSOP Pin Configuration 08076-040 VDD 1 Figure 5. LFCSP Pin Configuration Table 10. Pin Function Descriptions Pin No.
PAGE 11
Data Sheet AD5272/AD5274 TYPICAL PERFORMANCE CHARACTERISTICS 0.8 0.8 +125°C +25°C –40°C 0.6 RAW = 20kΩ TA = 25°C 0.4 0.2 0.2 0 0 –0.2 –0.2 0 128 256 384 512 640 768 896 –0.4 08076-010 –0.4 1023 CODE (Decimal) 0 256 512 CODE (Decimal) 768 1023 08076-111 INL (LSB) 0.4 INL (LSB) 20kΩ 50kΩ 100kΩ 0.6 Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5272) Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5272) 0.6 0.2 TA = 25°C RAW = 20kΩ 0.1 0.
PAGE 12
AD5272/AD5274 Data Sheet 0.15 0.15 +125°C +25°C –40°C 0.10 RAW = 20kΩ 20kΩ 50kΩ 100kΩ TA = 25°C 0.10 0.05 DNL (LSB) DNL (LSB) 0.05 0 0 –0.05 –0.05 –0.10 –0.10 0 128 256 384 512 640 768 896 1023 CODE (Decimal) –0.20 08076-015 –0.15 Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature (AD5272) 0 256 512 CODE (Decimal) 768 Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5272) 0.15 0.20 +125°C +25°C –40°C 0.15 1023 08076-122 –0.
PAGE 13
Data Sheet AD5272/AD5274 0.15 0.10 +125°C +25°C –40°C 0.08 RAW = 20kΩ 20kΩ 100kΩ TA = 25°C 0.10 0.05 INL (LSB) INL (LSB) 0.06 0.04 0 0.02 –0.05 0 64 128 CODE (Decimal) 192 255 –0.10 0 128 CODE (Decimal) 192 255 Figure 21. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5274) Figure 18. R-INL in Normal Mode vs. Code vs. Temperature (AD5274) 0.010 0.03 +125°C +25°C –40°C RAW = 20kΩ 0.02 TA = 25°C 100kΩ 20kΩ 0.008 0.01 DNL (LSB) 0.006 0.004 –0.01 0.002 –0.02 0 –0.
PAGE 14
AD5272/AD5274 Data Sheet 50 45 VDD/VSS = 5V/0V 20kΩ 50kΩ 100kΩ 20kΩ 50kΩ 100kΩ 6 THEORETICAL IWA_MAX (mA) 40 35 30 25 20 15 10 5 4 3 2 1 5 256 64 512 128 CODE (Decimal) 768 192 1023 AD5272 255 AD5274 0 0 08076-019 0 0 256 64 Figure 24. Tempco ΔRWA/ΔT vs. Code 768 192 1023 AD5272 255 AD5274 Figure 27. Theoretical Maximum Current vs.
PAGE 15
Data Sheet AD5272/AD5274 0 0 20kΩ 50kΩ 100kΩ VDD/VSS = 5V/0V CODE = HALF SCALE fIN = 1kHz NOISE BW = 22kHz –10 –20 –40 20kΩ 50kΩ 100kΩ –30 THD + N (dB) THD + N (dB) VDD/VSS = 5V/0V CODE = HALF SCALE NOISE BW = 22kHz –20 VIN = 1V rms –40 –50 –60 –60 –70 –80 –80 10k 08076-025 1k –100 0.001 100k FREQUENCY (Hz) Figure 30. THD + N vs. Frequency 0.01 0.1 VOLTAGE (VRMS) 08076-026 –90 –100 100 1 Figure 33. THD + N vs. Amplitude 0.03 0.
PAGE 16
AD5272/AD5274 Data Sheet 0.006 8 VDD/VSS = 5V/0V IAW = 10µA CODE = HALF SCALE 0.005 ΔRAW RESISTANCE (%) 6 5 0.004 0.003 0.002 0.001 0 4 0.07 0.09 0.11 0.13 0.15 TIME (Seconds) 0.17 –0.002 Figure 36. VEXT_CAP Waveform While Writing Fuse 0 100 200 300 400 500 600 700 800 900 1000 OPERATION AT 150°C (Hours) Figure 37. Long-Term Drift Accelerated Average by Burn-In Rev. D | Page 16 of 28 08076-038 –0.
PAGE 17
Data Sheet AD5272/AD5274 TEST CIRCUITS Figure 38 to Figure 42 define the test conditions used in the Specifications section. DUT DUT IW VMS 08076-033 VMS Figure 41. Gain vs. Frequency Figure 38. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) RWA = CODE = 0x00 IW V 08076-036 A A DUT 1GΩ W W DUT VMS IW GND ICM W RWA RW = 2 +2.75V –2.75V A W GND VMS NC = NO CONNECT +2.75V Figure 39. Wiper Resistance V+ = VDD ±10% IW W V+ PSS (%/%) = –2.75V Figure 42.
PAGE 18
AD5272/AD5274 Data Sheet THEORY OF OPERATION The AD5272 and AD5274 digital rheostats are designed to operate as true variable resistors for analog signals within the terminal voltage range of VSS < VTERM < VDD. The RDAC register contents determine the resistor wiper position. The RDAC register acts as a scratchpad register, which allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting using the I2C interface.
PAGE 19
Data Sheet AD5272/AD5274 Two bytes of data are then written to the RDAC, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the AD5272/AD5274. A stop condition follows. The write operations for the AD5272/ AD5274 are shown in Figure 43. WRITE OPERATION It is possible to write data for the RDAC register or the control register.
PAGE 20
AD5272/AD5274 Data Sheet A stop condition follows. These bytes contain the read instruction, which enables readback of the RDAC register, 50-TP memory, or the control register. The user can then read back the data beginning with a start command followed by an address byte (R/W = 1), after which the device acknowledges that it is prepared to transmit data by pulling SDA low. Two bytes of data are then read from the device, as shown in Figure 45. A stop condition follows.
PAGE 21
Data Sheet AD5272/AD5274 RDAC REGISTER Prior to 50-TP activation, the AD5272/AD5274 is preset to midscale on power-up. It is possible to read back the contents of any of the 50-TP memory registers through the I2C interface by using Command 5 in Table 12. The lower six LSB bits, D0 to D5 of the data byte, select which memory location is to be read back. A binary encoded version address of the most recently programmed wiper memory location can be read back using Command 6 in Table 12.
PAGE 22
AD5272/AD5274 Data Sheet Table 13. Write and Read to RDAC and 50-TP memory DIN 0x1C03 0x0500 0x0800 0x0C00 SDO1 0xXXXX 0x1C03 0x0500 0x100 0x1800 0x0000 0x0C00 0xXX19 0x1419 0x2000 0x0000 0x0100 0x0000 0xXXXX 1 Action Enable update of wiper position and 50-TP memory contents through digital interface. Write 0x100 to the RDAC register, wiper moves to ¼ full-scale position. Prepare data read from RDAC register. Stores RDAC register content into 50-TP memory.
PAGE 23
Data Sheet AD5272/AD5274 50-TP MEMORY WRITE-ACKNOWLEDGE POLLING A After each write operation to the 50-TP registers, an internal write cycle begins. The I2C interface of the device is disabled. To determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C interface polling can be conducted by sending a start condition, followed by the slave address and the write bit.
PAGE 24
AD5272/AD5274 Data Sheet EXT_CAP CAPACITOR A 1 μF capacitor to VSS must be connected to the EXT_CAP pin (see Figure 47) on power-up and throughout the operation of the AD5272/AD5274. AD5272/ AD5274 EXT_CAP C1 1µF 50_OTP MEMORY BLOCK POWER-UP SEQUENCE 08076-009 VSS VSS The ground pins of the AD5272/AD5274 devices are primarily used as digital ground references. To minimize the digital ground bounce, join the AD5272/AD5274 ground terminal remotely to the common ground.
PAGE 25
Data Sheet AD5272/AD5274 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 49. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 BOTTOM VIEW TOP VIEW 0.
PAGE 26
AD5272/AD5274 Data Sheet ORDERING GUIDE Model1 AD5272BRMZ-20 AD5272BRMZ-20-RL7 AD5272BRMZ-50 AD5272BRMZ-50-RL7 AD5272BRMZ-100 AD5272BRMZ-100-RL7 AD5272BCPZ-20-RL7 AD5272BCPZ-100-RL7 AD5274BRMZ-20 AD5274BRMZ-20-RL7 AD5274BRMZ-100 AD5274BRMZ-100-RL7 AD5274BCPZ-20-RL7 AD5274BCPZ-100-RL7 EVAL-AD5272SDZ 1 RAW (kΩ) 20 20 50 50 100 100 20 100 20 20 100 100 20 100 Resolution 1,024 1,024 1,024 1,024 1,024 1,024 1,024 1,024 256 256 256 256 256 256 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C
PAGE 27
Data Sheet AD5272/AD5274 NOTES Rev.
PAGE 28
AD5272/AD5274 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08076-0-3/13(D) Rev.