Datasheet

AD5273
Rev. H | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
W 1
V
DD
2
GND 3
SCL 4
A 8
B 7
AD0 6
SDA 5
AD5273
TOP VIEW
(Not to Scale)
03224-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 W Wiper Terminal W. GND ≤ V
W
≤ V
DD
.
2 V
DD
Positive Power Supply. Specified for non-OTP operation from 2.7 V to 5.5 V. For OTP programming, V
DD_OTP
must be set within the window of 5 V to 5.5 V for the 1 kΩ (DD8) and 10 kΩ (DD9) options, or within the
window of 4.75 V to 5.25 V for the 50 kΩ (DYG) and 100 kΩ (DYH) options, and be capable of sourcing 100 mA.
3 GND Common Ground.
4 SCL
Serial Clock Input. Requires a pull-up resistor. If it is driven directly from a logic controller without the pull-up
resistor, ensure that the V
IH
minimum is 0.7 × V
DD
.
5 SDA
Serial Data Input/Output. Requires a pull-up resistor. If it is driven directly from a logic controller without the
pull-up resistor, ensure that the V
IH
minimum is 0.7 × V
DD
.
6 AD0 I
2
C Device Address Bit. Allows a maximum of two AD5273 devices to be addressed.
7 B Resistor Terminal B. GND ≤ V
B
≤ V
DD
.
8 A Resistor Terminal A. GND ≤ V
A
≤ V
DD
.