Datasheet

AD5273
Rev. H | Page 17 of 24
I
2
C CONTROLLER PROGRAMMING
Write Bit Patterns
ACK. BY
AD5273
ACK. BY
AD5273
ACK. BY
AD5273
SDA
FRAME 1
SLAVE ADDRESS BYTE
SCL
STOP BY
MASTER
S
TART B
Y
MASTER
0
0
1
0
11
0
AD0
R/W
0
X
X
X
X
X
X
X
X
XD5
D4 D3 D2 D1
D0
80
80 8
FRAME 2
INSTRUCTION BYTE
FRAME 1
DATA BYTE
03224-043
Figure 42. Writing to the RDAC Register
ACK. BY
AD5273
ACK. BY
AD5273
ACK. BY
AD5273
FRAME 1
SLAVE ADDRESS BYTE
STOP BY
MASTER
S
TART B
Y
MASTER
FRAME 2
INSTRUCTION BYTE
FRAME 1
DATA BYTE
03224-044
SDA
SCL
0
0
1
0
11
0
AD0
R/W
1
X
X
X
X
X
XX
X
X D5D4D3D2D1
D0
8
0
8
08
Figure 43. Activating One-Time Programming
Read Bit Pattern
ACK. BY
AD5273
NO ACK. BY
AD5273
FRAME 1
SLAVE ADDRESS BYTE
STOP BY
MASTER
S
TART B
Y
MASTER
FRAME 2
DATA BYTE FROM SELECTED
RDAC REGISTER
03224-059
SDA
SCL
0
1
0
11
0
AD0
R/W
E1
E0 D5 D4 D3 D2 D1
D0
0
8
08
Figure 44. Reading Data from the RDAC Register
For users who do not use the software solution, the AD5273 can
be controlled via an I
2
C-compatible serial bus and is connected
to this bus as a slave device. Referring to Figure 42, Figure 43,
and Figure 44, the 2-wire I
2
C serial bus protocol operates as
follows:
1.
The master initiates data transfer by establishing a start
condition. A start condition is defined as a high-to-low
transition on the SDA line while SCL is high, as shown in
Figure 42. The byte following the start condition is the
slave address byte, which consists of six MSBs defined as
010110. The next bit is AD0; it is an I
2
C device address bit.
Depending on the states of the AD0 bits, two AD5273s can
be addressed on the same bus, as shown in Figure 45. The
last LSB is the R/
W
bit, which determines whether data is
read from or written to the slave device.
The slave address corresponding to the transmitted address
responds by pulling the SDA line low during the ninth
clock pulse (this is termed the acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register.
2.
A write operation contains one more instruction byte than
the read operation. The instruction byte in the write mode
follows the slave address byte. The MSB of the instruction
byte labeled T is the OTP bit. After acknowledging the
instruction byte, the last byte in the write mode is the data
byte. Data is transmitted over the serial bus in sequences of
nine clock pulses (eight data bits followed by an acknowl-
edge bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL, as shown in Figure 42.
3.
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is trans-
mitted over the serial bus in sequences of nine clock pulses
(slight difference from write mode, there are eight data bits
followed by a no acknowledge bit). Similarly, the transitions
on the SDA line must occur during the low period of SCL
and remain stable during the high period of SCL, as shown
in Figure 44.