Datasheet

Data Sheet AD5270/AD5271
Rev. F | Page 7 of 24
INTERFACE TIMING SPECIFICATIONS
V
DD
= 2.5 V to 5.5 V, V
SS
= 0 V; V
DD
= 2.5 V, V
SS
= −2.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 7.
Parameter Limit
1
Unit Test Conditions/Comments
t
1
2
20 ns min SCLK cycle time
t
2
10 ns min SCLK high time
t
3
10 ns min SCLK low time
t
4
15 ns min
SYNC
to SCLK falling edge setup time
t
5
5 ns min Data setup time
t
6
5 ns min Data hold time
t
7
1 ns min
SCLK falling edge to SYNC
rising edge
t
8
3, 4
500 ns min
Minimum SYNC
high time
t
9
15 ns min
SYNC
rising edge to next SCLK fall ignored
t
10
5
450 ns max SCLK rising edge to SDO valid
t
RDAC_R-PERF
2 μs max RDAC register write command execute time
t
RDAC_NORMAL
600 ns max RDAC register write command execute time
t
MEMORY_READ
6 μs max Memory readback execute time
t
MEMORY_PROGRAM
350 ms max Memory program time
t
RESET
0.6 ms max Reset 50-TP restore time
t
POWER-UP
6
2 ms max Power-on 50-TP restore time
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency is 50 MHz.
3
Refer to t
RDAC_R-PER
and t
RDAC_NORMAL
for RDAC register write operations.
4
Refer to t
MEMORY_READ
and
t
MEMORY_PROGRAM
for memory commands operations.
5
R
PULL_UP
= 2.2 kΩ to V
DD
with a capacitance load of 168 pF.
6
Maximum time after V
DD
− V
SS
is equal to 2.5 V.
Shift Register and Timing Diagrams
DATA BITS
DB9 (MSB) DB0 (LSB)
D7 D6 D5 D4 D3
D2 D1
D0
CONTROL BITS
C0C1
C2
D9
D8
C3
00
08077-002
Figure 2. Shift Register Content
0 0 C3 C2 D7 D6 D5 D2 D1 D0
SCLK
SDO
DIN
SYNC
t
7
t
9
t
1
t
2
t
4
t
3
t
8
t
5
t
6
08077-003
Figure 3. Write Timing Diagram (CPOL = 0, CPHA = 1)