Datasheet

AD5270/AD5271 Data Sheet
Rev. F | Page 22 of 24
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—1% Resistor Tolerance
The nominal resistance between Terminal W and Terminal A, R
WA
,
is 20 kΩ, 50 kΩ, or 100 kΩ and has 1024-/256-tap points accessed
by the wiper terminal. The 10-/8-bit data in the RDAC latch is
decoded to select one of the 1024 or 256 possible wiper settings.
The AD5270 and AD5271 contain an internal ±1% resistor
tolerance calibration feature that can be disabled or enabled,
enabled by default, or by programming Bit C2 of the control
register (see Table 13 and Table 14).
The digitally programmed output resistance between the W
terminal and the A terminal, R
WA
, is calibrated to give a
maximum of ±1% absolute resistance error over both the full
supply and temperature ranges. As a result, the general
equations for determining the digitally programmed output
resistance between the W terminal and the A terminal are the
following:
For the AD5270
WAWA
R
D
DR 
1024
)(
(1)
For the AD5271
WAWA
R
D
DR 
256
)(
(2)
where:
D is the decimal equivalent of the binary code loaded in the
10-/8-bit RDAC register.
R
WA
is the end-to-end resistance.
In the zero-scale condition, a finite total wiper resistance of
120 Ω is present. Regardless of which setting the part is oper-
ating in, take care to limit the current between Terminal A to
Terminal W to the maximum continuous current of ±3 mA or
a pulse current specified in Table 8. Otherwise, degradation or
possible destruction of the internal switch contact can occur.
EXT_CAP CAPACITOR
A 1 μF capacitor to V
SS
must be connected to the EXT_CAP
pin, as shown in Figure 46, on power-up and throughout the
operation of the AD5270/AD5271.
AD5270/
AD5271
50_OTP
MEMORY
BLOCK
EXT_CAP
C1
1µF
V
SS
V
SS
08077-008
Figure 46. EXT_CAP Hardware Setup
TERMINAL VOLTAGE OPERATING RANGE
The positive V
DD
and negative V
SS
power supplies of the
AD5270/AD5271 define the boundary conditions for proper
2-terminal digital resistor operation. Supply signals present on
Term in a l A and Te rmina l W th at exce ed V
DD
or V
SS
are clamped
by the internal forward-biased diodes, see Figure 47.
V
SS
V
DD
A
W
08077-009
Figure 47. Maximum Terminal Voltages Set by V
DD
and V
SS
The ground pins of the AD5270/AD5271 devices are primarily
used as digital ground references. To minimize the digital ground
bounce, join the AD5270/AD5271 ground terminal remotely
to the common ground. The digital input control signals to the
AD5270/AD5271 must be referenced to the device ground pin
(GND), and must satisfy the logic level defined in the
Specifications section. An internal level shift circuit ensures that
the common-mode voltage range of the three terminals extends
from V
SS
to V
DD
, regardless of the digital input level.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A and Terminal W (see Figure 47), it is important to
power V
DD
/V
SS
first before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that V
DD
/V
SS
are powered unintentionally. The ideal power-up
sequence is V
SS
, GND, V
DD
, digital inputs, V
A
, and V
W
. The
order of powering V
A
, V
W
, and the digital inputs is not
important as long as they are powered after V
DD
/V
SS
.
As soon as V
DD
is powered, the power-on preset activates which
first sets the RDAC to midscale and then restores the last pro-
grammed 50-TP value to the RDAC register.