Datasheet

Data Sheet AD5270/AD5271
Rev. F | Page 21 of 24
Table 15. Memory Map
Command Number
Data Byte[DB9:DB8]
1
Register Contents D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
5 X X X 0 0 0 0 0 0 0 Reserved
X X X 0 0 0 0 0 0 1 1st programmed wiper location (0x01)
X X X 0 0 0 0 0 1 0 2nd programmed wiper location (0x02)
X X X 0 0 0 0 0 1 1 3rd programmed wiper location (0x03)
X X X 0 0 0 0 1 0 0 4th programmed wiper location (0x04)
… … … … … … … … … … …
X X X 0 0 0 1 0 1 0 10th programmed wiper location (0xA)
X X X 0 0 1 0 1 0 0 20th programmed wiper location (0x14)
X X X 0 0 1 1 1 1 0 30th programmed wiper location (0x1E)
X X X 0 1 0 1 0 0 0 40th programmed wiper location (0x28)
X X X 0 1 1 0 0 1 0 50th programmed wiper location (0x32)
1
X is don’t care.
SDO PIN AND DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can be
used to read the contents of the wiper setting and 50-TP values
using Command 2 and Command 5, respectively (see Table 11),
or the SDO pin can be used in daisy-chain mode. Data is clocked
out of SDO on the rising edge of SCLK. The SDO pin contains
an open-drain N-channel FET that requires a pull-up resistor.
To place the pin in high impedance and mini-mize the power
dissipation when the pin is used, the 0x8001 data word followed
by Command 0 should be sent to the part. Table 16 provides a
sample listing for the sequence of the serial data input (DIN).
Daisy chaining minimizes the number of port pins required
from the controlling IC. As shown in Figure 44, the user must
tie the SDO pin of one package to the DIN pin of the next
package. The user may need to increase the clock period because
the pull-up resistor and the capacitive loading at the SDO-to-
DIN interface may require additional time delay between
subsequent devices. When two AD5270/AD5271 devices are
daisy-chained, 32 bits of data are required. The first 16 bits go to
U2, and the second 16 bits go to U1.
Table 16. Minimize Power Dissipation at the SDO Pin
DIN SDO
1
Action
0xXXXX 0xXXXX Last user command sent to the digipot.
0x8001 0xXXXX
Prepares the SDO pin to be placed in
high impedance mode.
0x0000
High
Impedance
The SDO pin is placed in high
impedance.
1
X is don’t care.
Keep the
SYNC
pin low until all 32 bits are clocked to their
respective serial registers. The
SYNC
pin is then pulled high to
complete the operation.
MOSI
SSSCLK
SDO
SCLK
DINDIN SDO
AD5270/
AD5271
U1
AD5270/
AD5271
U2
SYNC
SCLK
SYNC
V
DD
µC
R
P
2.2kΩ
08077-006
Figure 44. Daisy-Chain Configuration Using SDO
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices has patented
the RDAC segmentation architecture for all the digital potentio-
meters. In particular, the AD5270/AD5271 employ a three-stage
segmentation approach as shown in Figure 45.The AD5270/
AD5271 wiper switch is designed with the transmission gate
CMOS topology.
A
W
8-/10-BIT
ADDRESS
DECODER
R
L
R
L
R
M
R
M
R
W
S
W
R
W
08077-007
Figure 45. Simplified RDAC Circuit