Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Electrical Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions
- Timing Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions
- Absolute Maximum Ratings
- Pin Configuration and Pin Function Descriptions
- Typical Performance Characteristics
- Test Circuits
- SPI-Compatible Digital Interface (DIS = 0)
- I2C-Compatible Digital Interface (DIS = 1)
- Operation
- Programming the Variable Resistor
- Programming the Potentiometer Divider Voltage Output Operation
- Pin-Selectable Digital Interface
- SPI-Compatible 3-Wire Serial Bus (DIS = 0)
- I2C-Compatible 2-Wire Serial Bus (DIS = 1)
- Additional Programmable Logic Output
- Self-Contained Shutdown Function
- Multiple Devices on One Bus
- Level Shift for Negative Voltage Operation
- ESD Protection
- Terminal Voltage Operating Range
- Power-Up Sequence
- VLOGIC Power Supply
- Layout and Power Supply Bypassing
- RDAC Circuit Simulation Model
- Applications Information
- Bipolar DC or AC Operation from Dual Supplies
- Gain Control Compensation
- Programmable Voltage Reference
- 8-Bit Bipolar DAC
- Bipolar Programmable Gain Amplifier
- Programmable Voltage Source with Boosted Output
- Programmable 4 to 20 mA Current Source
- Programmable Bidirectional Current Source
- Programmable Low-Pass Filter
- Programmable Oscillator
- Resistance Scaling
- Resistance Tolerance, Drift, and Temperature Coefficient Mismatch Considerations
- Outline Dimensions
Data Sheet AD5263
Rev. F | Page 17 of 28
OPERATION
The AD5263 is a quad-channel, 256-position, digitally
controlled, variable resistor (VR) device.
To program the VR settings, refer to the SPI-Compatible Digital
Interface (DIS = 0) section and the I2C-Compatible Digital
Interface (DIS = 1) section. The part has an internal power-on
preset that places the wiper at midscale during power-on,
simplifying the fault condition recovery at power-up. In addition,
the shutdown (
SHDN
) pin of AD5263 places the RDAC in an
almost zero-power consumption state where Terminal A is
open circuited and the wiper W is connected to Terminal B,
resulting in only leakage current consumption in the VR structure.
During shutdown, the VR latch settings are maintained or new
settings can be programmed. When the part is returned from
shutdown, the corresponding VR setting is applied to the RDAC.
03142-044
Bx
Wx
Ax
SD BIT
D7
D6
D4
D5
D2
D3
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
Figure 45. AD5263 Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 20 kΩ, 50 kΩ, and 200 kΩ. The final
two or three digits of the part number determine the nominal
resistance value, for example, 20 kΩ = 20; 50 kΩ = 50;
200 kΩ = 200. The nominal resistance (R
AB
) of the VR has
256 contact points accessed by the wiper terminal, plus the B
terminal contact. The 8-bit data in the RDAC latch is decoded to
select one of the 256 possible settings. Assuming a 20 kΩ part is
used, the wiper’s first connection starts at the B terminal for data
0x00. Because there is a 60 Ω wiper contact resistance, such a
connection yields a minimum of 2 × 60 Ω resistance between the
W and B terminals. The second connection is the first tap point,
and corresponds to 198 Ω (R
WB
= R
AB
/256 + R
W
= 78 Ω + 2 ×
60 Ω) for Data 0x01. The third connection is the next tap point
representing 276 Ω (R
WB
= 78 Ω × 2 + 2 × 60 Ω) for Data 0x02,
and so on. Each LSB data value increase moves the wiper up the
resistor ladder until the last tap point is reached at 20,042 Ω
(R
AB
– 1 LSB + 2 × R
W
). Figure 45 shows a simplified diagram of
the equivalent RDAC circuit, where the last resistor string is not
accessed; therefore, there is 1 LSB less of the nominal resistance at
full scale in addition to the wiper resistance.
The general equation determining the digitally programmed
output resistance between the W and B terminals is
W
AB
WB
RR
D
DR ×+×= 2
256
)(
(1)
where:
D is the decimal equivalent of the binary code loaded in the 8-bit
RDAC register.
R
AB
is the end-to-end resistance.
R
W
is the wiper resistance contributed by the on-resistance of one
internal switch.
In summary, if R
AB
= 20 kΩ and the A terminal is open circuited,
the RDAC latch codes in Table 5 result in the corresponding output
resistance, R
WB
.
Table 5. Codes and Corresponding R
WB
Resistances
D (Dec)
R
WB
(Ω)
Output State
255 20,042 Full-scale (R
AB
− 1 LSB + 2 × R
W
)
128 10,120 Midscale
1 198 1 LSB + 2 × R
W
0 120 Zero-scale (wiper contact resistance)
Note that in the zero-scale condition a finite wiper resistance of
120 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the W wiper and Terminal A also produces a
digitally controlled complementary resistance, R
WA
. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for R
WA
starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
ABWA
RR
D
DR ×+×
−
= 2
256
256
)(
(2)
For R
AB
= 20 kΩ and the B terminal is open circuited, the RDAC
latch codes in Table 6 result in the corresponding output
resistance R
WA
.
Table 6. Codes and Corresponding R
WA
Resistances
D (Dec)
R
WA
(Ω) Output State
255 198 Full scale
128 10,120 Midscale
1 20,042 1 LSB + 2 × R
W
0 20,120 Zero scale