Datasheet

AD5263 Data Sheet
Rev. F | Page 22 of 28
V
LOGIC
POWER SUPPLY
The AD5263 is capable of operating at high voltages beyond the
internal logic levels, which are limited to operation at 5 V. As a
result, V
L
always needs to be tied to a separate 2.7 V to 5.5 V source
to ensure proper digital signal levels. Logic levels must be limited to
V
L
, regardless of V
DD
. In addition, V
L
should always be less than
or equal to V
DD
.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 µF to 0.1 µF ceramic
disc or chip capacitors. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 55). Notice the digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
03142-055
GND
V
SS
V
DD
AD5263
V
SS
V
DD
C1
0.1µF
C2
0.1µF
C3
10µF
C4
10µF
+
+
Figure 55. Power Supply Bypassing
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive loads
dominate the ac characteristics of the RDACs. Configured as a
potentiometer divider, the –3 dB bandwidth of the AD5263 (20 kΩ
resistor) measures 300 kHz at half scale. Figure 22 provides the
large signal BODE plot characteristics of the three available
resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simulation
model is shown in Figure 56. The following code provides a
macro model net list for the 20 kΩ RDAC.
03142-069
20kΩ
C
A
W
25pF
RDAC
A B
C
B
C
W
25pF
55pF
Figure 56. RDAC Circuit Simulation Model for RDAC = 20 k
Ω
Listing 1. Macro Model Net List for RDAC
.PARAM D=256, RDAC=20E3
*
.SUBCKT DPOT (A,W,B)
*
CA A 0 25E-12
RWA A W {(1-D/256)*RDAC+60}
CW W 0 55E-12
RWB W B {D/256*RDAC+60}
CB B 0 25E-12
*
.ENDS DPOT