Datasheet

AD5263
Rev. 0 | Page 4 of 28
TIMING CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS
(V
DD
= +5 V, V
SS
= –5 V, V
L
= +5 V, V
A
= +V
DD
, V
B
= 0 V, –40°C < T
A
< +125°C unless otherwise noted.)
Table 2.
Parameter Symbol Conditions Min Typ
1
Max Unit
SPI INTERFACE TIMING CHARACTERISTICS (Specifications Apply to All Parts
6, 13
)
Clock Frequency f
CLK
25 MHz
Input Clock Pulsewidth t
CH
,t
CL
Clock level high or low 20 ns
Data Setup Time t
DS
10 ns
Data Hold Time t
DH
10 ns
CS
Setup Time
t
CSS
15 ns
CS
High Pulsewidth
t
CSW
20 ns
CLK Fall to
CS
Fall Hold Time
t
CSH0
0 ns
CLK Fall to
CS
Rise Hold Time
t
CSH1
0 ns
CS
Rise to Clock Rise Setup
t
CS1
10 ns
Reset Pulsewidth t
RS
5 ns
I
2
C INTERFACE TIMING CHARACTERISTICS (Specifications Apply to All Parts
6, 13
)
SCL Clock Frequency f
SCL
400 kHz
t
BUF
Bus Free Time between STOP and START t
1
1.3 µs
t
HD;STA
Hold Time (Repeated START) t
2
After this period, the first clock
pulse is generated.
0.6 µs
t
LOW
Low Period of SCL Clock t
3
1.3 µs
t
HIGH
High Period of SCL Clock t
4
0.6 50 µs
t
SU;STA
Setup Time for START Condition t
5
0.6 µs
t
HD;DAT
Data Hold Time t
6
0.9 µs
t
SU;DAT
Data Setup Time t
7
100 ns
t
F
Fall Time of both SDA and SCL Signals t
8
300 ns
t
R
Rise Time of Both SDA and SCL Signals t
9
300 ns
t
SU;STO
Setup Time for STOP Condition t
10
0.6 µs
NOTES
1
Typicals represent average readings at 25°C and V
DD
= +5 V, V
SS
= –5 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
= +5 V and
V
SS
= –5 V.
3
V
AB
= V
DD
, Wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8
V
L
is limited to V
DD
or 5.5 V, whichever is less.
9
Worst-case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
10
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
11
All dynamic characteristics use V
DD
= +5 V, V
SS
= –5 V, V
L
= +5 V.
12
Settling time depends on value of V
DD
, R
L
, and C
L
.
13
See timing diagrams for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of +3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using V
L
= +5 V.