Datasheet

AD5263
Rev. 0 | Page 18 of 28
When V
IN
is high, Q1 is turned on and its emitter is clamped at
one threshold above ground. This threshold appears at the base
of Q2, which causes Q2 to turn off. In this state, V
OUT
approaches –5 V. When V
IN
is low, Q1 is turned off and the base
of Q2 is pulled low, which in turn causes Q2 to turn on. In this
state, V
OUT
approaches 0 V. Beware that proper time shifting is
also needed for successful communication with the device.
03142-0-054
A
V
DD
B
W
V
SS
03142-0-051
V
IN
R3
R1
R2
10kΩ
V
OUT
–5V
10kΩ
–5V
1kΩ
Q2
2N3906
Q1
2N3906
+
5V
0V
–5V
0V
Figure 53. Maximum Terminal Voltages Set by V
DD
and V
SS
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
Terminals A, B, and W (see Figure 53), it is important to power
V
DD
and V
SS
before applying any voltage to Terminals A, B, and
W; otherwise, the diodes will be forward biased such that V
DD
and V
SS
will be powered unintentionally and may affect the rest
of the circuit. The ideal power-up sequence is in the following
order: GND, V
DD
, V
SS
, V
L
, digital inputs, and V
A/B/W
. The relative
order of powering V
A
, V
B
, V
W
, and digital inputs is not
important as long as they are powered after V
DD
and V
SS
.
Figure 50. Level Shift for Bipolar Potential Operation
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 51 and Figure 52.
This protection applies to digital input pins SDI/SDA,
CLK/SCL,
CS
/AD0,
RES
/AD1, and
SHDN
.
V
LOGIC
POWER SUPPLY
The AD5263 is capable of operating at high voltages beyond the
internal logic levels, which are limited to operation at 5 V. As a
result, V
L
always needs to be tied to a separate 2.7 V to 5.5 V
source to ensure proper digital signal levels. Logic levels must
be limited to V
L
, regardless of V
DD
. In addition, V
L
should always
be less than or equal to V
DD
.
03142-0-052
LOGIC
340Ω
V
SS
LAYOUT AND POWER SUPPLY BYPASSING
Figure 51. ESD Protection of Digital Pins
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
03142-0-053
A,B,W
V
SS
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF ceramic disc
or chip capacitors. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 54). Notice the digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
Figure 52. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5263 positive V
DD
and negative V
SS
power supply defines
the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminals A,
B, and W that exceed V
DD
or V
SS
will be clamped by the internal
forward biased diodes shown in Figure 53.
03142-0-055
GND
V
SS
V
DD
AD5263
V
SS
V
DD
C1
C2
C3
C4
10µF
10µF
0.1µF
0.1µF
+
+
Figure 54. Power Supply Bypassing