Datasheet

AD5263
4. After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition (see Figure 42). In read mode, the master will
issue a no acknowledge for the ninth clock pulse (i.e., the
SDA line remains high). The master will then bring the
SDA line low before the tenth clock pulse, which goes high
to establish a STOP condition (see Figure 43).
03142-0-047
R
PULL-DOWN
SCL
O1
SHDN
SDA
AD5263
Figure 47. Shutdown by Internal Logic Output
MULTIPLE DEVICES ON ONE BUS
Figure 48 shows four AD5263 devices on the same serial bus.
Each has a different slave address since the states of their AD0
and AD1 pins are different. This allows each RDAC within each
device to be written to or read from independently. The master
device output bus line drivers are open-drain pull-downs in a
fully I
2
C compatible interface.
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and
instructing the part only once. For example, after the RDAC has
acknowledged its slave address and instruction bytes in the
write mode, the RDAC output will update on each successive
byte. If different instructions are needed, the write/read mode
has to start again with a new slave address, instruction, and data
byte. Similarly, a repeated read function of the RDAC is also
allowed.
03142-0-048
MASTER
AD5263
SDA SCL
R
P
R
P
+5V
SDA
SCL
AD0
+5V
SDA SCL
AD5263
AD0
+5V
SDA SCL
AD5263
AD0
+5V
SDA SCL
AD5263
AD0
AD1 AD1 AD1 AD1
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
The AD5263 features additional programmable logic outputs,
O1 and O2, which can be used to drive a digital load, analog
switches, and logic gates. O1 and O2 default to Logic 0. The
voltage level can swing from GND to V
L
. The logic states of O1
and O2 can be programmed in Frame 2 under write mode (see
Figure 42). These logic outputs have adequate current driving
capability to sink/source milliamperes of load.
Figure 48. Multiple AD5263 Devices on One I
2
C Bus
LEVEL SHIFT FOR NEGATIVE VOLTAGE
OPERATION
Users can also activate O1 and O2 in three different ways
without affecting the wiper settings. They may do the following:
The digital potentiometer is popular in laser diode driver and
certain telecommunication equipment level-setting applications.
These applications are sometimes operated between ground and
some negative supply voltage so that the systems can be biased
at ground to avoid large bypass capacitors that may significantly
impede the ac performance. Like most digital potentiometers,
the AD5263 can be configured with a negative supply (see
Figure 49).
1. START, slave address byte, acknowledge, instruction byte with
O1 and O2 specified, acknowledge, STOP.
2. Complete the write cycle with STOP, then START, slave
address byte, acknowledge, instruction byte with O1 and O2
specified, acknowledge, STOP.
3. Do not complete the write cycle by not issuing the STOP, then
START, slave address byte, acknowledge, instruction byte with
O1 and O2 specified, acknowledge, STOP.
03142-0-050
SDA
GND
V
SS
V
DD
SCL
LEVEL SHIFTED
LEVEL SHIFTED
–5V
AD5263
SELF-CONTAINED SHUTDOWN FUNCTION
Shutdown can be activated by strobing the
SHDN
pin or
programming the SD bit in the write mode instruction byte. In
addition, shutdown can even be implemented with the device’s
digital output as shown in Figure 47. In this configuration, the
device will be shut down during power-up, but users are allowed
to program the device. Thus, when O1 is programmed high, the
device will exit from the shutdown mode and respond to the
new setting. This self-contained shutdown function allows
absolute shutdown during power-up, which is crucial in
hazardous environments, without adding extra components.
Figure 49. Biased at Negative Voltage
However, the digital inputs must also be level shifted to allow
proper operation since the ground is now referenced to the
negative potential. As a result, Figure 50 shows one
implementation with a couple transistors and a few resistors.
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