Datasheet

AD5263
Rev. 0 | Page 13 of 28
I
2
C COMPATIBLE DIGITAL INTERFACE (DIS = 1)
Table 5. I
2
C Write Mode Data-Word Format
S 0 1 0 1 1 AD1 AD0 W
A X A1 A0 RS SD O1 O2 X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Instruction Byte Data Byte
Table 6. I
2
C Read Mode Data-Word Format
S 0 1 0 1 1 AD1 AD0 R A D7 D8 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
S = Start condition.
P = Stop condition.
A = Acknowledge.
AD1, AD0 = I
2
C device address bits. Must match with the logic
states at pins AD1, AD0. Refer to Figure 48.
A1, A0 = RDAC channel select.
RS = Software reset wiper (A1, A0) to midscale position.
SD = Shutdown active high; ties wiper (A1, A0) to Terminal A,
opens Terminal B, RDAC register contents are not disturbed. To
exit shutdown, the command SD = 0 must be executed for each
RDAC (A1, A0).
O1, O2 = Data to digital output pins O1, O2 in I
2
C mode, used
to drive external logic. The logic high level is determined by V
L
and the logic low level is GND.
W
= Write = 0.
R = Read = 1.
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.
X = Don’t Care.
03142-0-041
SCL
S
D
A
PS
P
S
t
8
t
9
t
9
t
8
t
3
t
2
t
1
t
4
t
7
t
5
t
10
t
2
Figure 41. Detailed I
2
C Timing Diagram
03142-0-042
SCL
FRAME 1 FRAME 2
START B
Y
MASTER
ACK BY
AD5263
SLAVE ADDRESS BYTE
STOP BY
MASTER
INSTRUCTION BYTE
SDA
0
1
0
1
1 AD1 AD0 R/W
XA1 RSSDO1O2X
1 919
D7 D6 D5 D4 D3 D2 D1 D0
ACK BY
AD5263
FRAME 3
DATA BYTE
19
ACK BY
AD5263
A0
Figure 42
. Writing to the RDAC Register
03142-0-043
NO ACK
BY MASTER
SCL
SDA
0 1 0 1 1 AD1 AD0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
1 919
FRAME 1
FRAME 2
S
TART B
Y
MASTER
ACK BY
AD5263
SLAVE ADDRESS BYTE
RDAC REGISTER
STOP BY
MASTER
Figure 43. Reading Data from a Previously Selected RDAC Register in Write Mode