Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - Digital potentiometer linear Non-permanent TSSOP 24

Quad, 15 V, 256-Position, Digital

Potentiometer with Pin Selectable SPI/I

AD5263

Rev. 0

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FEATURES

256-position, 4-channel

End-to-end resistance 20 kΩ, 50 kΩ, 200 kΩ

Pin selectable SPI® or I

C® compatible interface

Power-on preset to midscale

Two package address decode pins AD0 and AD1

Rheostat mode temperature coefficient 30 ppm/°C

Voltage divider temperature coefficient 5 ppm/°C

Wide operating temperature range –40°C to +125°C

5 V to 15 V single supply; ±5 V dual supply

APPLICATIONS

Mechanical potentiometer replacement

Optical network adjustment

Instrumentation: gain, offset adjustment

Stereo channel audio level control

Automotive electronics adjustment

Programmable power supply

Programmable filters, delays, time constants

Line impedance matching

Low resolution DAC/trimmer replacement

Base station power amp biasing

Sensor calibration

GENERAL DESCRIPTION

The AD5263 is the industry’s first quad-channel, 256-position,

digital potentiometer

with a selectable digital interface. This

device performs the same electronic adjustment function as

mechanical potentiometers or variable resistors, with enhanced

resolution, solid-state reliability, and superior low temperature

coefficient performance.

Each channel of the AD5263 offers a completely programmable

value of resistance between the A terminal and the wiper, or

between the B terminal and the wiper. The fixed A-to-B

terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has a nominal

temperature coefficient of ±30 ppm/°C and a ±1% channel-to-

channel matching tolerance. Another key feature of this part is

the ability to operate from +4.5 V to +15 V, or at ±5 V.

Wiper position programming presets to midscale upon power-

on. Once powered, the VR wiper position is programmed by

either the 3-wire SPI or 2-wire I

C compatible interface. In the

C mode, additional programmable logic outputs enable users

to drive digital loads, logic gates, and analog switches in their

systems.

The AD5263 is available in a narrow body TSSOP-24. All parts

are guaranteed to operate over the automotive temperature

range of –40°C to +125°C.

For single- or dual-channel applications, refer to the

AD5260/AD5280 or AD5262/AD5282.

FUNCTIONAL BLOCK DIAGRAM

03142-0-001

SERIAL INPUT

AD5263

ADDRESS

DECODER

SPI/I

SELECT

LOGIC

RDAC 4

RDAC 3

RDAC 1

RDAC 2

GND

W1 B1 A2

W2 B2

B3 A4

W4 B4

CS/AD0

SDI/SDA

CLK/SCL

SHDN

RES/AD1

DIS

NC/O2

SDO/O1

Figure 1.

The terms digital potentiometer, VR, and RDAC are used interchangeably.

Purchase of licensed I

C components of Analog Devices or one of its sublicensed

Associated Companies conveys a license for the purchaser under the Philips I

Patent Rights to use these components in an I

C system, provided that the system

conforms to the I

C Standard Specification as defined by Philips.

Summary of content (28 pages)

PAGE 1
Quad, 15 V, 256-Position, Digital Potentiometer with Pin Selectable SPI/I2C AD5263 256-position, 4-channel End-to-end resistance 20 kΩ, 50 kΩ, 200 kΩ Pin selectable SPI® or I2C® compatible interface Power-on preset to midscale Two package address decode pins AD0 and AD1 Rheostat mode temperature coefficient 30 ppm/°C Voltage divider temperature coefficient 5 ppm/°C Wide operating temperature range –40°C to +125°C 5 V to 15 V single supply; ±5 V dual supply APPLICATIONS Mechanical potentiometer replacement
PAGE 2
AD5263 TABLE OF CONTENTS Electrical Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions ....... 3 Applications..................................................................................... 20 Timing Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions........... 4 Bipolar DC or AC Operation from Dual Supplies................. 20 Absolute Maximum Ratings............................................................ 5 Gain Control Compensation ....................................................
PAGE 3
AD5263 ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS (VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.) Table 1. Parameter Symbol Conditions DC CHARACTERISTICS—RHEOSTAT MODE (Specifications apply to all VRs.
PAGE 4
AD5263 TIMING CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS (VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +VDD, VB = 0 V, –40°C < TA < +125°C unless otherwise noted.) Table 2.
PAGE 5
AD5263 ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) Table 3. Parameter VDD to GND VSS to GND VDD to VSS VL to GND VA, VB, VW to GND Terminal Current, Ax-Bx, Ax-Wx, Bx-Wx Pulsed1 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJ MAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Vapor Phase (60 sec) Infrared (15 sec) Thermal Resistance2 θJA TSSOP-24 Value –0.3 V to +16.5 V 0 V to +7.5 V +16.5 V –0.3 V to +6.
PAGE 6
AD5263 TYPICAL PERFORMANCE CHARACTERISTICS (RAB = 20 kΩ unless otherwise noted.) 1 1 ±5V 0.8 –40°C 25°C 85°C 125°C 0.8 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 32 64 96 128 160 192 224 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 03142-0-004 RHEOSTAT MODE INL (LSB) 0.6 0.4 03142-0-073 RHEOSTAT MODE DNL (LSB) 15/0V –0.8 –1 0 256 32 64 1 0.8 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 64 96 128 160 192 224 256 192 224 ±5V 15/0V 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.
PAGE 7
AD5263 1 2 –40°C 25°C 85°C 125°C 1.6 1.4 0.2 1.2 ZSE (LSB) 0.4 0 –0.2 0.8 0.6 –0.6 0.4 –1 0 32 64 96 128 160 192 224 VDD/VSS = ±5V 1 –0.4 –0.8 VDD/VSS = 4.5/0V VDD/VSS = 16.5/0V 03142-0-010 0.6 1.8 03142-0-007 0.2 0 –40 256 –20 0 CODE (Decimal) 60 80 100 120 Figure 11. Zero-Scale Error vs. Temperature 10 1 0.6 IDD/ISS SUPPLY CURRENT (µA) –40°C 25°C 85°C 125°C 0.8 0.4 0.2 0 –0.2 –0.4 VLOGIC = 5V VIH = 5V VIL = 0V 1 ISS @ VDD/VSS = ±5V 0.1 0.
PAGE 8
AD5263 27 VDD/VSS = 15/0V 25 VDD/VSS = ±5V 24 03142-0-013 23 22 –40 40 0 0 –50 –100 –150 –200 –250 0 120 80 50 32 64 96 85 RON @ VDD/VSS = 5/0V 224 256 0x20 –18 GAIN (dB) 70 RON @ VDD/VSS = ±5V 60 0x08 –30 0x04 –36 0x02 –42 RON @ VDD/VSS = 15/0V 55 0x10 –24 0x01 03142-0-014 –48 50 45 –5 0 5 10 TA = 25°C VA = 50mV rms VDD/VSS = ±5V –54 –60 1k 15 10k 100k 03142-0-017 65 0x80 0x40 –12 75 1M FREQUENCY (Hz) VBIAS (V) Figure 18. Gain vs. Frequency vs.
PAGE 9
AD5263 0 0x80 –6 –12 0x20 –18 0x10 –24 0x08 –30 VW 1 0x04 –36 0x02 –42 TA = 25°C VA = 50mV rms VDD/VSS = ±5V –54 –60 1k 10k 03142-0-022 0x01 –48 03142-0-019 GAIN (dB) Code = 0x80 VDD/VSS = ±5.5V VB/VA= ±5V 0x40 Ch 1 100k 50.0mV FREQUENCY (Hz) M 100ns A CH2 2.70 V Figure 23. Digital Feedthrough Figure 20. Gain vs. Frequency vs.
PAGE 10
AD5263 1 2 RAB = 20kΩ TA = 25°C 1 0.5 Avg – 3σ Avg Avg – 3σ R-INL (LSB) INL (LSB) RAB = 20kΩ TA = 25°C 1.5 0 0.5 Avg + 3σ Avg Avg – 3σ 0 –0.5 03142-0-025 –1 0 5 10 15 03142-0-026 –1 –0.5 –1.5 –2 0 20 |VDD – VSS| (–V) 5 10 15 |VDD – VSS| (V) Figure 26. INL vs. Supply Voltage Figure 27. R-INL vs. Supply Voltage Rev.
PAGE 11
AD5263 TEST CIRCUITS A A VIN V+ = VDD 1LSB = V+/2N DUT DUT AD8610 OFFSET GND B 2.5V B 03142-0-028 W V+ VMS +15V W VOUT 03142-0-034 Figure 28 to Figure 38 define the test conditions used in the product specification table. –15V Figure 34. Test Circuit for Gain vs Frequency Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) NO CONNECT DUT A RSW = DUT CODE = 0x00 W IW W B 0.1V ISW 0.1V ISW 03142-0-029 VSS TO VDD Figure 35.
PAGE 12
AD5263 SPI COMPATIBLE DIGITAL INTERFACE (DIS = 0) Addr B9 B8 A1 A0 29 Data B7 B6 D7 D6 MSB 27 B5 D5 B4 D4 B3 D3 B2 D2 SDI B1 D1 CLK B0 D0 LSB 20 CS VOUT 1 A1 A0 D7 D6 D5 D3 D4 D2 D1 D0 0 1 0 RDAC REGISTER LOAD 1 0 03142-0-039 Table 4. AD5263 Serial Data-Word Format 1 0 Figure 39. AD5263 Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) 1 SDI Dx (DATA IN) Dx 0 tCH 1 tDS tCH tCS1 CLK 0 tCSHO tCL tCSH1 tCSS 1 CS tC-SW 0 tS 0 ±LSB Figure 40.
PAGE 13
AD5263 I2C COMPATIBLE DIGITAL INTERFACE (DIS = 1) Table 5. I2C Write Mode Data-Word Format S 0 1 0 1 1 AD1 AD0 W A X A1 A0 Slave Address Byte RS SD O1 O2 X A D7 D6 D5 D4 Instruction Byte D3 D2 D1 D0 A P Data Byte Table 6. I2C Read Mode Data-Word Format S 0 1 0 1 1 AD1 AD0 Slave Address Byte R A D7 D8 D5 D4 D3 Data Byte D2 D1 D0 A P S = Start condition. P = Stop condition. A = Acknowledge.
PAGE 14
AD5263 OPERATION The AD5263 is a quad-channel, 256-position, digitally controlled, variable resistor (VR) device. therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. To program the VR settings, refer to the interface sections of the previous pages. The part has an internal power-on preset that places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up.
PAGE 15
AD5263 The typical distribution of the end-to-end resistance RAB from channel to channel matches within ±1%. Device to device matching is process lot dependent and is possible to have ±30% variation. Since the resistance element is processed in thin film technology, the change in RAB with temperature has a very low temperature coefficient of 30 ppm/°C. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation Table 9.
PAGE 16
AD5263 The fourth MSB (RS) is the midscale reset. A logic high on this bit moves the wiper of the selected channel to the center tap where RWA = RWB. This feature effectively writes over the contents of the register, so that when taken out of reset mode, the RDAC will remain at midscale. Figure 46). If two AD5263s are daisy-chained, a total of 20 bits of data is required. The first 10 bits, complying with the format shown in Table 4, go to U2 and the second 10 bits, with the same format, go to U1.
PAGE 17
AD5263 After all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 42). In read mode, the master will issue a no acknowledge for the ninth clock pulse (i.e., the SDA line remains high).
PAGE 18
AD5263 VDD When VIN is high, Q1 is turned on and its emitter is clamped at one threshold above ground. This threshold appears at the base of Q2, which causes Q2 to turn off. In this state, VOUT approaches –5 V. When VIN is low, Q1 is turned off and the base of Q2 is pulled low, which in turn causes Q2 to turn on. In this state, VOUT approaches 0 V. Beware that proper time shifting is also needed for successful communication with the device. 0V B R3 VSS 03142-0-054 VIN W 1kΩ Figure 53.
PAGE 19
AD5263 RDAC CIRCUIT SIMULATION MODEL Listing 1. Macro Model Net List for RDAC The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider, the –3 dB bandwidth of the AD5263 (20 kΩ resistor) measures 300 kHz at half scale. Figure 21 provides the large signal BODE plot characteristics of the three available resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simulation model is shown in Figure 55.
PAGE 20
AD5263 APPLICATIONS BIPOLAR DC OR AC OPERATION FROM DUAL SUPPLIES The AD5263 can be operated from dual supplies, enabling control of ground referenced ac signals or bipolar operation. The ac signal, as high as VDD/VSS, can be applied directly across Terminals A-B with the output taken from Terminal W. See Figure 56 for a typical circuit connection. +5.0V VDD SCL SDA SCLK MCSI 5Vp-p A1 W1 GND B1 2.
PAGE 21
AD5263 8-BIT BIPOLAR DAC Figure 59 shows a low cost, 8-bit, bipolar DAC. It offers the same number of adjustable steps but not the precision as compared to conventional DACs. The linearity and temperature coefficient, especially at low values codes, are skewed by the effects of the digital potentiometer wiper resistance.
PAGE 22
AD5263 PROGRAMMABLE 4–20 mA CURRENT SOURCE A programmable 4–20 mA current source can be implemented with the circuit shown in Figure 62. The REF191 is a unique low supply headroom and high current handling precision reference that can deliver 20 mA at +2.048 V.
PAGE 23
AD5263 PROGRAMMABLE LOW-PASS FILTER PROGRAMMABLE OSCILLATOR In A/D conversion applications, it is common to include an antialiasing filter to band-limit the sampling signal. Dualchannel digital potentiometers can be used to construct a second order Sallen-Key low-pass filter (see Figure 64). The design equations are In a classic Wien-bridge oscillator (Figure 65), the Wien network (R, R′, C, C′) provides positive feedback, while R1 and R2 provide negative feedback.
PAGE 24
AD5263 The AD5263 offers 20kΩ, 50kΩ, and 200kΩ nominal resistances. Users who need a lower resistance and the same number of step adjustments can place multiple devices in parallel. For example, Figure 66 shows a simple scheme of using two channels in parallel. To adjust half of the resistance linearly per step, users need to program both channels to the same settings.
PAGE 25
AD5263 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION B1 1 24 B2 23 A2 22 W2 B3 4 21 B4 A3 5 20 A4 W3 6 19 W4 W1 3 VDD 7 GND 8 DIS 9 AD5263 TSSOP-24 18 VSS TOP VIEW 17 NC/O2 (Not to Scale) 16 SDO/O1 VLOGIC 10 15 SHDN SDI/SDA 11 14 RES/AD1 CLK/SCL 12 13 CS/AD0 03142-0-072 A1 2 Figure 71. 24-Lead TSSOP PIN FUNCTION DESCRIPTIONS Table 11.
PAGE 26
AD5263 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 1 6.40 BSC 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MS-153AD Figure 72. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ESD CAUTION ESD (electrostatic discharge) sensitive device.
PAGE 27
AD5263 NOTES Rev.