Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Table of Contents
- Electrical Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions
- Timing Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions
- Absolute Maximum Ratings
- Pin Configuration and Pin Function Descriptions
- Typical Performance Characteristics
- Test Circuits
- SPI-Compatible Digital Interface (DIS = 0)
- I2C-Compatible Digital Interface (DIS = 1)
- Operation
- Programming the Variable Resistor
- Programming the Potentiometer Divider Voltage Output Operation
- Pin-Selectable Digital Interface
- SPI-Compatible 3-Wire Serial Bus (DIS = 0)
- I2C-Compatible 2-Wire Serial Bus (DIS = 1)
- Additional Programmable Logic Output
- Self-Contained Shutdown Function
- Multiple Devices on One Bus
- Level Shift for Negative Voltage Operation
- ESD Protection
- Terminal Voltage Operating Range
- Power-Up Sequence
- VLOGIC Power Supply
- Layout and Power Supply Bypassing
- RDAC Circuit Simulation Model
- Applications Information
- Bipolar DC or AC Operation from Dual Supplies
- Gain Control Compensation
- Programmable Voltage Reference
- 8-Bit Bipolar DAC
- Bipolar Programmable Gain Amplifier
- Programmable Voltage Source with Boosted Output
- Programmable 4 to 20 mA Current Source
- Programmable Bidirectional Current Source
- Programmable Low-Pass Filter
- Programmable Oscillator
- Resistance Scaling
- Resistance Tolerance, Drift, and Temperature Coefficient Mismatch Considerations
- Outline Dimensions
AD5263 Data Sheet
Rev. F | Page 4 of 28
Parameter Symbol Conditions Min Typ
1
Max Unit
POWER SUPPLIES
Logic Supply
8
V
L
2.7 5.5 V
Power Single-Supply Range V
DD RANGE
V
SS
= 0 V 4.5 16.5 V
Power Dual-Supply Range V
DD/SS RANGE
±4.5 ±7.5 V
Logic Supply Current
9
I
L
V
L
= +5 V
25
60
µA
Positive Supply Current I
DD
V
IH
= +5 V or V
IL
= 0 V 1 µA
Negative Supply Current I
SS
V
SS
= –5 V 1 µA
Power Dissipation
10
P
DISS
V
IH
= +5 V or V
IL
= 0 V, V
DD
=
+5 V, V
SS
= –5 V
0.6 mW
Power Supply Sensitivity PSS ∆V
DD
= +5 V ± 10% 0.002 0.01 %/%
DYNAMIC CHARACTERISTICS
6, 11
Bandwidth (3 dB) BW R
AB
= 20 kΩ/50 kΩ/200 kΩ 300/150/35 kHz
Total Harmonic Distortion THD
W
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz,
R
AB
= 20 kΩ
0.05 %
V
W
Settling Time
12
t
S
V
A
= 10 V, V
B
= 0 V, ±1 LSB error
band
2 µs
Resistor Noise Voltage e
N_WB
R
WB
= 10 kΩ, f = 1 kHz, RS = 0 9
nV/√
Hz
1
Typicals represent average readings at +25°C and V
DD
= +5 V, V
SS
= −5 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
= +5 V and
V
SS
= –5 V.
3
V
AB
= V
DD
, Wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
V
L
is limited to V
DD
or 5.5 V, whichever is less.
9
Worst-case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
10
P
DISS
is calculated from I
DD
× V
DD
. CMOS logic level inputs result in minimum power dissipation.
11
All dynamic characteristics use V
DD
= +5 V, V
SS
= −5 V, V
L
= +5 V.
12
Settling time depends on value of V
DD
, R
L
, and C
L
.