Datasheet

AD5260/AD5262
Rev. A | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5260
NC = NO CONNECT
1
2
3
4
5
6
7
W
B
V
DD
SDI
CLK
S
HDN
A
14
13
12
11
10
9
8
NC
V
L
V
SS
CS
PR
GND
SDO
TOP VIEW
(Not to Scale)
0
2695-008
Figure 7. AD5260 Pin Configuration
Table 5. AD5260 Pin Function Descriptions
Pin No. Mnemonic Description
1 A A Terminal.
2 W Wiper Terminal.
3 B B Terminal.
4 V
DD
Positive Power Supply. Specified for operation at both 5 V or 15 V (sum of |V
DD
| + |V
SS
| ≤ 15 V).
5
SHDN
Active Low Input. Terminal A, open-circuit. Shutdown controls variable resistor.
6 CLK Serial Clock Input, Positive Edge Triggered.
7 SDI Serial Data Input.
8
CS
Chip Select Input, Active Low. When CS
returns high, data is loaded into the RDAC register.
9
PR
Active Low Preset to Midscale. Sets RDAC registers to 0x80.
10 GND Ground.
11 V
SS
Negative Power Supply. Specified for operation from 0 V to −5 V.
12 V
L
Logic Supply Voltage. Needs to be the same voltage as the digital logic controlling the AD5260.
13 NC No Connect. Users should not connect anything other than a dummy pad on this pin.
14 SDO Serial Data Output. Open-drain transistor requires a pull-up resistor.