Datasheet

AD5260/AD5262
Rev. A | Page 18 of 24
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ a compact, minimum lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance (see Figure 55). Note that
the digital ground should also be joined remotely to the analog
ground to minimize the ground bounce.
V
SS
V
DD
V
SS
V
DD
C3
C4
C1
C2
10µF
10µF
GND
0.1µF
0.1µF
+
+
02695-053
Figure 55. Power Supply Bypassing
TERMINAL VOLTAGE OPERATING RANGE
The AD5260/AD5262 positive V
DD
and negative V
SS
power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on the
A, B, and W terminals that exceed V
DD
or V
SS
are clamped by
the internal forward-biased diodes (see Figure 56).
V
DD
V
SS
A
W
B
02695-054
Figure 56. Maximum Terminal Voltages Set by V
DD
and V
SS
The ground pin of the AD5260/AD5262 device is primarily
used as a digital ground reference, which needs to be tied to the
common ground of the PCB. The digital input control signals to
the AD5260/AD5262 must be referenced to the device ground
pin (GND), and must satisfy the logic level defined in Tabl e 1 .
An internal level shift circuit ensures that the common-mode
voltage range of the three terminals extends from V
SS
to V
DD
regardless of the digital input level.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 56), it is
important to power V
DD
/V
SS
first before applying any voltage to
the A, B, and W terminals. Otherwise, the diode becomes forward
biased such that V
DD
/V
SS
are powered unintentionally and may
affect the rest of the user’s circuit. The ideal power-up sequence
is in the following order: GND, V
DD
, V
SS
, V
L
, the digital inputs,
and V
A
/V
B
/V
W
. The order of powering V
A
/V
B
/V
W
and the digital
inputs is not important as long as they are powered after V
DD
/V
SS
.
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the −3 dB bandwidth of the AD5260
(20 kΩ resistor) measures 310 kHz at half scale. Figure 28 provides
the large signal Bode plot characteristics of the three available
resistor versions 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simula-
tion model is shown in Figure 57. The following section provides a
macro model net list for the 20 kΩ RDAC.
AB
55pF
C
B
25pF
C
A
25pF
C
W
RDAC
20kΩ
W
02695-071
Figure 57. RDAC Circuit Simulation Model for RDAC 20 kΩ
MACRO MODEL NET LIST FOR RDAC
PARAM D=256, RDAC=20E3
*
SUBCKT DPOT (A,W,B)
*
CA A 0 25E-12
RWA A W {(1-D/256)*RDAC+60}
CW W 0 55E-12
RWB W B {D/256*RDAC+60}
CB B 0 25E-12
*
.ENDS DPOT