Datasheet

AD5260/AD5262
Rev. A | Page 4 of 24
Parameter Symbol Conditions Min Typ
1
Max Unit
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB BW R
AB
= 20 kΩ/50 kΩ/200 kΩ 310/130/30 kHz
Total Harmonic Distortion THD
W
V
A
= 1 V
RMS
, V
B
= 0 V, f = 1 kHz,
R
AB
= 20 kΩ
0.014 %
V
W
Settling Time t
S
V
A
= +5 V, V
B
= −5 V, ±1 LSB
error band, R
AB
= 20 kΩ
5 μs
Crosstalk
11
C
T
V
A
= V
DD
, V
B
= 0 V, measure V
W
with adjacent RDAC making
full-scale code change (AD5262
only)
1 nV-sec
Analog Crosstalk C
TA
V
A1
= V
DD
, V
B1
= 0 V, measure V
W1
with V
W2
= 5 V p-p at f = 10 kHz,
R
AB
= 20 kΩ/200 kΩ (AD5262
only)
–64 dB
Resistor Noise Voltage e
N_WB
R
WB
= 20 kΩ, f = 1 kHz 13 nV/√Hz
INTERFACE TIMING CHARACTERISTICS
6, 12
Specifications apply to all parts
Clock Frequency f
CLK
25 MHz
Input Clock Pulse Width t
CH
, t
CL
Clock level high or low 20 ns
Data Setup Time t
DS
10 ns
Data Hold Time t
DH
10 ns
CLK to SDO Propagation Delay
13
t
PD
R
L
= 1 kΩ, C
L
< 20 pF 1 160 ns
CS
Setup Time
t
CSS
5 ns
CS
High Pulse Width
t
CSW
20 ns
Reset Pulse Width t
RS
50 ns
CLK Fall to
CS
Rise Hold Time
t
CSH
0 ns
CS
Rise to Clock Rise Setup
t
CS1
10 ns
1
Typical values represent average readings at 25°C and V
DD
= +5 V, V
SS
= −5 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
= +5 V and
V
SS
= −5V.
3
V
AB
= V
DD
, wiper = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8
Worst-case supply current consumed when all logic-input levels set at 2.4 V, which is the standard characteristic of CMOS logic.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V
DD
= +5 V, V
SS
= −5 V, V
L
= +5 V.
11
Measured at V
W
where an adjacent V
W
is making a full-scale voltage change.
12
See Figure 5 for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using V
L
= 5 V.
13
Propagation delay depends on value of V
DD
, R
L
, and C
L
.