Datasheet

Data Sheet AD5259
Rev. C | Page 5 of 24
TIMING CHARACTERISTICS
V
DD
= V
LOGIC
= 5 V ± 10% or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
I
2
C INTERFACE TIMING
CHARACTERISTICS
1
SCL Clock Frequency f
SCL
0 400 kHz
t
BUF
Bus Free Time Between Stop
and Start
t
1
1.3 μs
t
HD;STA
Hold Time (Repeated Start) t
2
After this period, the first clock pulse is
generated.
0.6 μs
t
LOW
Low Period of SCL Clock t
3
1.3 μs
t
HIGH
High Period of SCL Clock t
4
0.6 μs
t
SU;STA
Setup Time for Repeated
Start Condition
t
5
0.6 μs
t
HD;DAT
Data Hold Time t
6
0 0.9 μs
t
SU;DAT
Data Setup Time t
7
100 ns
t
F
Fall Time of Both SDA and
SCL Signals
t
8
300 ns
t
R
Rise Time of Both SDA and
SCL Signals
t
9
300 ns
t
SU;STO
Setup Time for Stop Condition t
10
0.6 μs
EEPROM Data Storing Time t
EEMEM_STORE
26 ms
EEPROM Data Restoring Time at
Power On
2
t
EEMEM_RESTORE1
V
DD
rise time dependent. Measure without
decoupling capacitors at V
DD
and GND.
300 μs
EEPROM Data Restoring Time upon
Restore Command
2
t
EEMEM_RESTORE2
V
DD
= 5 V. 300 μs
EEPROM Data Rewritable Time
3
t
EEMEM_REWRITE
540 μs
FLASH/EE MEMORY RELIABILITY
Endurance
4
100 700 kCycles
Data Retention
5
100 Years
1
Standard I
2
C mode operation guaranteed by design.
2
During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
3
Delay time after power-on PRESET prior to writing new EEPROM data.
4
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +125°C; typical endurance at +25°C is 700,000 cycles.
5
Retention lifetime equivalent at junction temperature (T
J
) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
05026-004
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
PS S
SCL
SDA
P
Figure 4. I
2
C Interface Timing Diagram