Datasheet

AD5258
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS
V
DD
= V
LOGIC
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +85°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
I
2
C INTERFACE TIMING CHARACTERISTICS
SCL Clock Frequency f
SCL
0 400 kHz
t
BUF
Bus Free Time between STOP and START t
1
1.3 µs
t
HD;STA
Hold Time (Repeated START) t
2
After this period, the first clock pulse is
generated.
0.6 µs
t
LOW
Low Period of SCL Clock t
3
1.3 µs
t
HIGH
High Period of SCL Clock t
4
0.6 µs
t
SU;STA
Setup Time for Repeated START
Condition
t
5
0.6 µs
t
HD;DAT
Data Hold Time t
6
0 0.9 µs
t
SU;DAT
Data Setup Time t
7
100 ns
t
F
Fall Time of Both SDA and SCL Signals t
8
300 ns
t
R
Rise Time of Both SDA and SCL Signals t
9
300 ns
t
SU;STO
Setup Time for STOP Condition t
10
0.6 µs
EEPROM Data Storing Time t
EEMEM_STORE
26 ms
EEPROM Data Restoring Time at Power On
1
t
EEMEM_RESTORE1
V
DD
rise time dependant. Measure
without decoupling capacitors at V
DD
and
GND.
300 µs
EEPROM Data Restoring Time upon Restore
Command
1
t
EEMEM_RESTORE2
V
DD
= 5 V. 300 µs
EEPROM Data Rewritable Time
2
t
EEMEM_REWRITE
540 µs
FLASH/EE MEMORY RELIABILITY
Endurance
3
100 700 kCycles
Data Retention
4
100 Years
1
During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
2
Delay time after power-on PRESET prior to writing new EEPROM data.
3
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
4
Retention lifetime equivalent at junction temperature (T
J
) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates
with junction temperature.
05029-004
t
1
SCL
SDA
PS P
t
3
t
2
t
8
t
9
t
8
t
9
t
4
t
5
t
7
t
6
t
10
Figure 4. I
2
C Interface Timing Diagram