Datasheet

AD5258
Rev. 0 | Page 19 of 24
ESD PROTECTION OF DIGITAL PINS AND
RESISTOR TERMINALS
The AD5258 V
DD
, V
LOGIC
, and GND power supplies define the
boundary conditions for proper 3-terminal and digital input
operation. Supply signals present on Terminal A, Terminal B,
and Terminal W that exceed V
DD
or GND are clamped by the
internal forward biased ESD protection diodes (see Figure 41).
Digital Input SCL and Digital Input SDA are clamped by ESD
protection diodes with respect to V
LOGIC
and GND as shown in
Figure 42.
GND
A
W
B
V
DD
05029-039
Figure 41. Maximum Terminal Voltages Set by V
DD
and GND
GND
SCL
SDA
V
LOGIC
05029-040
Figure 42. Maximum Terminal Voltages Set by V
LOGIC
and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Term ina l A, Ter mina l B, a nd Ter minal W (s ee Figure 41) , it is
important to power GND/V
DD
/V
LOGIC
before applying any
voltage to Terminal A, Terminal B, and Terminal W; otherwise,
the diode is forward biased such that V
DD
and V
LOGIC
are
powered unintentionally and may affect the user’s circuit. The
ideal power-up sequence is in the following order: GND, V
DD
,
V
LOGIC
, digital inputs, and then V
A
, V
B
, V
W
. The relative order of
powering V
A
, V
B
, V
W
, and the digital inputs is not important as
long as they are powered after GND/V
DD
/V
LOGIC
.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with minimum conductor length. Ground paths should
have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic
capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum
or electrolytic capacitors should also be applied at the supplies
to minimize any transient disturbance and low frequency ripple
(see Figure 43). The digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
V
DD
GND
V
DD
C2
10µF
C1
0.1µF
AD5258
+
05029-041
Figure 43. Power Supply Bypassing
MULTIPLE DEVICES ON ONE BUS
The AD5258 has two three-state configurable Address Pins
AD0 and AD1. The state of these two pins is registered upon
power-up and decoded into a corresponding I
2
C 7-bit address
(see Table 5). This allows up to nine devices on the bus to be
written to, or read from, independently. In the case that the pin
is assigned to be floated, the static voltage will be V
LOGIC
/2.
EVALUATION BOARD
An evaluation board, along with all necessary software, is
available to program the AD5258 from any PC running
Windows® 98/2000/XP. The graphical user interface, as shown
in Figure 44, is straightforward and easy to use. More detailed
information is available in the user manual that comes with the
board.
05029-042
Figure 44. AD5258 Evaluation Board Software